HD404639R Datasheet, PDF (34/135 Pages) Renesas Technology Corp – 4-Bit Single-Chip Microcomputer

HD404639R Series
Direct Transition from Subactive Mode to Active Mode: Available by controlling the direct transfer on
flag (DTON: $020, bit 3) and the low speed on flag (LSON: $020, bit 0). The procedures are described
below:
• Set LSON to 0 and DTON to 1 in subactive mode.
• Execute the STOP or SBY instruction.
• The MCU automatically enters active mode from subactive mode after waiting for the MCU internal
processing time and oscillation stabilization time (figure 19).
Notes: 1. The DTON flag ($020, bit 3) can be set only in subactive mode. It is always reset in active
mode.
2. The transition time (T_D) from subactive mode to active mode:
t_RC < T_D < T + t_RC
STOP/SBY instruction execution
Subactive mode
MCU internal
processing period
(Set LSON = 0, DTON = 1)
Oscillation
stabilization
time
Active mode
Interrupt strobe
Direct transfer
completion timing
T
t _RC
T_D
T: Interrupt frame length
t_RC: Oscillation stabilization period
T_D: Transition time
Figure 19 Direct Transition Timing
Stop Mode Cancellation by STOPC: The MCU enters active mode from stop mode by a STOPC input as
well as by RESET. In either case, the MCU starts instruction execution from the starting address (address
0) of the program. However, the value of the RAM enable flag (RAME: $021, bit 3) differs between
cancellation by STOPC and by RESET. When stop mode is cancelled by RESET, RAME = 0; when
cancelled by STOPC, RAME = 1. RESET can cancel all modes, but STOPC is valid only in stop mode;
STOPC input is ignored in other modes. Therefore, when the program requires to confirm that stop mode
has been cancelled by STOPC (for example, when the RAM contents before entering stop mode are used
after transition to active mode), execute the TEST instruction on the RAM enable flag (RAME) at the
beginning of the program.
MCU Operation Sequence: The MCU operates in the sequences shown in figures 20 to 22. It is reset by
an asynchronous RESET input, regardless of its status.
The low-power mode operation sequence is shown in figure 22. With the IE flag cleared and an interrupt
flag set together with its interrupt mask cleared, if a STOP/SBY instruction is executed, the instruction is
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