HD404639R Datasheet, PDF (32/135 Pages) Renesas Technology Corp – 4-Bit Single-Chip Microcomputer

 HD404639R Series
Oscillator
Internal
clock
Stop mode
RESET
STOPC
t_res
STOP instruction execution
t_res ≥ t_RC (stabilization period)
Figure 16 Timing of Stop Mode Cancellation
Subactive Mode: The OSC₁ and OSC₂ oscillator stops and the MCU operates with a clock generated by
the X1 and X2 oscillator. In this mode, functions other than the DTMF generator operate. However,
because the operating clock is slow, the power dissipation becomes low, next to watch mode.
The CPU instruction execution speed can be selected as 244 µs or 122 µs by setting bit 2 (SSR12) of
system clock select register 1 (SSR1: $029). Note that the SSR12 value must be changed in active mode.
If the value is changed in subactive mode, the MCU may malfunction.
When the STOP or SBY instruction is executed in subactive mode, the MCU enters either watch or active
mode, depending on the statuses of the low speed on flag (LSON: $020, bit 0) and the direct transfer on
flag (DTON: $020, bit 3).
Subactive mode is an optional function that the user must specify on the function option list.
Interrupt Frame: In watch and subactive modes, φ_CLK is applied to timer A and the INT₀ circuit.
Prescaler W and timer A operate as the time-base and generate the timing clock for the interrupt frame.
Three interrupt frame lengths (T) can be selected by setting the miscellaneous register (MIS: $00C) (figure
18).
In watch and subactive modes, the timer-A/INT₀ interrupt is generated synchronously with the interrupt
frame. The interrupt request is generated synchronously with the interrupt strobe timing except during
transition to active mode. The falling edge of the INT₀ signal is input asynchronously with the interrupt
frame timing, but it is regarded as input synchronously with the second interrupt strobe clock after the
falling edge. An overflow and interrupt request in timer A is generated synchronously with t he interrupt
strobe timing.
Note on Use: When the MCU is in watch mode or sub-active mode and if the high level period before the
falling edge of INT₀ is shorter than the interrupt frame or if the low level period after the falling edge of
INT₀ is shorter than the interrupt frame, INT₀ is not detected. Therefore, the high or low level period of
INT₀ must be held longer than the interrupt frame when the MCU is in watch mode or subactive mode.
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