HD404639R Datasheet, PDF (11/135 Pages) Renesas Technology Corp – 4-Bit Single-Chip Microcomputer

HD404639R Series
Bit 3
IM0
0
(IM of INT₀)
Bit 2
IF0
(IF of INT₀)
Bit 1
RSP
(Reset SP bit)
1
IMTA
(IM of timer A)
IFTA
(IF of timer A)
IM1
(IM of INT₁)
Bit 0
IE
(Interrupt
enable flag)
IF1
(IF of INT₁)
$000
$001
2
IMTC
(IM of timer C)
IFTC
(IF of timer C)
IMTB
(IM of timer B)
IFTB
(IF of timer B)
$002
IMS1
3 (IM of serial
interface 1)
IFS1
(IF of serial
interface 1)
IMTD
(IM of timer D)
IFTD
(IF of timer D)
$003
Interrupt control bits area
Bit 3
DTON
32 (Direct transfer
on flag)
RAME
33 (RAM enable
flag)
34
IM3
(IM of INT₃)
IMS2
35 (IM of serial
interface 2)
Bit 2
Not used
Not used
Bit 1
WDON
(Watchdog
on flag)
ICEF
(Input capture
error flag)
IF3
(IF of INT₃)
IFS2
(IF of serial
interface 2)
IM2
(IM of INT₂)
IM4
(IM of INT₄)
Register flag area
Bit 0
LSON
(Low speed
on flag)
ICSF
(Input capture
status flag)
IF2
(IF of INT₂)
IF4
(IF of INT₄)
$020
$021
$022
$023
IF: Interrupt request flag
IM: Interrupt mask
IE: Interrupt enable flag
SP: Stack pointer
Figure 3 Configuration of Interrupt Control Bits and Register Flag Areas
IE
IM
LSON
IF
ICSF
ICEF
RAME
RSP
WDON
DTON
Not used
SEM/SEMD
Allowed
Not executed
Not executed
Allowed
Not executed in active mode
Used in subactive mode
Not executed
REM/REMD
Allowed
Allowed
Allowed
Not executed
Allowed
Not executed
TM/TMD
Allowed
Allowed
Inhibited
Inhibited
Allowed
Inhibited
Note: WDON is reset by MCU reset or by STOPC enable for stop mode cancellation.
DTON is always reset in active mode.
If the TM or TMD instruction is executed for the inhibited bits or non-existing bits,
the value in ST becomes invalid.
Figure 4 Usage Limitations of RAM Bit Manipulation Instructions
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