HD404639R Datasheet, PDF (21/135 Pages) Renesas Technology Corp – 4-Bit Single-Chip Microcomputer

HD404639R Series
Instruction cycles
1
2
3
4
5
6
Instruction
execution ^*
Interrupt
acceptance
Stacking
IE reset
Vector address
generation
Execution of JMPL
instruction at vector address
Note: ^* The stack is accessed and the IE reset after the instruction
is executed, even if it is a two-cycle instruction.
Figure 10 Interrupt Processing Sequence
Execution of
instruction at
start address
of interrupt
routine
19