HD404639R Datasheet, PDF(10/135 Page) Renesas Technology Corp

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HD404639R Datasheet, PDF (10/135 Pages) Renesas Technology Corp – 4-Bit Single-Chip Microcomputer

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HD404639R Series

RAM-mapped registers

Memory registers (MR)

Not used

144

$000

$040

$050

$090

Data (464 digits Ã 2)

V = 0 (bank 0)

V = 1 (bank 1)

608

752

960

1023

Data (144 digits)

Not used

Stack (64 digits)

$260

$2F0

$3C0

$3FF

$090

Data

(464 digits)

V=0

(bank = 0)

Data

(464 digits)

V=1

(bank = 1)

$25F

Note: * The data area has two banks:

bank 0 (V = 0) to bank 1 (V = 1)

R: Read only

W: Write only

R/W: Read/Write

Two registers are mapped

on the same area.

Interrupt control bits area

4 Port mode register A

(PMRA) W

5 Serial mode register 1A (SM1A) W

6 Serial data register 1 lower (SR1L) R/W

7 Serial data register 1 upper (SR1U) R/W

8 Timer mode register A

(TMA) W

9 Timer mode register B1 (TMB1) W

10 Timer B

(TRBL/TWBL) R/W

(TRBU/TWBU) R/W

12 Miscellaneous register

(MIS) W

13 Timer mode register C1 (TMC1) W

14 Timer C

(TRCL/TWCL) R/W

(TRCU/TWCU) R/W

16 Timer mode register D1 (TMD1) W

17 Timer D

(TRDL/TWDL) R/W

(TRDU/TWDU) R/W

19 Timer mode register B2 (TMB2) R/W

20 Timer mode register C2 (TMC2) R/W

21 Timer mode register D2 (TMD2) R/W

22 Compare control register (CCR) W

23 Compare data register

(CDR) R

24 Compare enable register (CER) W

25 TG mode register

(TGM) W

26 TG control register

(TGC) W

27 Serial mode register 2A (SM2A) W

28 Serial mode register 2B (SM2B) W

29 Serial data register 2 lower (SR2L) R/W

30 Serial data register 2 upper (SR2U) R/W

Not used

36 Port mode register B

(PMRB) W

37 Port mode register C (PMRC) W

38 Detection edge select register 1 (ESR1) W

39 Detection edge select register 2 (ESR2) W

40 Serial mode register 1B (SM1B) W

41 System clock select register 1 (SSR1) W

42 System clock select register 2 (SSR2) W

Not used

44 Port D0 to D3 DCR

(DCD0) W

45 Port D4 to D7DCR

(DCD1) W

46 Port D8 to D11 DCR

(DCD2) W

Not used

48 Port R0 DCR

(DCR0) W

49 Port R1 DCR

(DCR1) W

50 Port R2 DCR

(DCR2) W

51 Port R3 DCR

(DCR3) W

52 Port R4 DCR

(DCR4) W

53 Port R5 DCR

(DCR5) W

54 Port R6 DCR

(DCR6) W

55 Port R7 DCR

(DCR7) W

56 Port R8 DCR

(DCR8) W

57 Port R9 DCR

(DCR9) W

58 Port RA DCR

(DCRA) W

59 Port RB DCR

(DCRB) W

60 Port RC DCR

(DCRC) W

Not used

63 V register

R/W

$000

$003

$004

$005

$006

$007

$008

$009

$00A

$00B

$00C

$00D

$00E

$00F

$010

$011

$012

$013

$014

$015

$016

$017

$018

$019

$01A

$01B

$01C

$01D

$01E

$01F

$020

$023

$024

$025

$026

$027

$028

$029

$02A

$02B

$02C

$02D

$02E

$02F

$030

$031

$032

$033

$034

$035

$036

$037

$038

$039

$03A

$03B

$03C

$03F

10 Timer read register B lower (TRBL) R Timer write register B lower (TWBL) W $00A

11 Timer read register B upper (TRBU) R Timer write register B upper (TWBU) W $00B

14 Timer read register C lower (TRCL) R Timer write register C lower (TWCL) W $00E

15 Timer read register C upper (TRCU) R Timer write register C upper (TWCU) W $00F

17 Timer read register D lower (TRDL) R Timer write register D lower (TWDL) W $011

18 Timer read register D upper (TRDU) R Timer write register D upper (TWDU) W $012

Figure 2 RAM Memory Map

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