HD6473258F10V Datasheet, PDF (83/301 Pages) Renesas Technology Corp – Hitachi Single-Chip Microcomputer

Interrupt
accepted
Interrupt priority
decision. Wait for Instruction Internal
end of instruction. fetch
process-
ing
Interrupt request
signal
Stack
Vector
table
fetch
Instruction fetch
(first instruction of
Internal interrupt-handling
process- routine)
ing
Ø
Internal address
bus
Internal Read
signal
Internal Write
signal
Internal 16-bit
data bus
(1)
(3)
(2)
(4)
(5)
(6)
(8)
(9)
(1)
(7)
(9)
(10)
(₍1₁)_{) In}I_sn_ts_rutr_cu_tic_ot_nio_pn_rep_fere_tcf_het_ac_dh_da_red_sd_sre_(Ps_us_s(_hP_eu_ds_oh_ne_sd_tao_cn_k.st_Ia_nc_stk_r._ucI_tn_ios_ntr_iu_sc_eti_xo_en_cuis_tee_dx_oe_nc_ru_et_te_ud_rno_fn_ror_meturn from
intⁱeⁿr^tr^eu^rp^rt^u-h^pa^t-n^hd^alinⁿg^dlrⁱoⁿu^gtin^roe^u.)^tine.)
(₍2₂)₎ (₍4₄)_{) Ins}In_trs_ut_cru_tioc_ntio_cn_odc_eo₍d_Ne_o(_tN_eo_xet _ce_ux_te_edc₎uted)
((33)) InIsntrsutrcuticotniopnrepferetcfhetacdhdaredsdsr(eNsost (eNxeoct uetxeed)cuted)
((55)) SPS–P2–2
(⁽6⁶)^{) SP}S^–P⁴–4
(⁽7⁷)^{) CC}C^RCR
(⁽8⁸)^{) Ad}A^dd^red^sre^ss^os^{f v}o^ef^cv^toe^rc^tt^ao^br^leta^ebⁿle^tryentry
(⁽9⁹)^{) Ve}V^ce^toc^rto^tar ^bta^leb^ele^nte^rynt⁽r^ay^dd(a^red^sd^sre^ofs^fs^irso^tf fⁱⁿir^ss^tt^ruin^cs^tiotrⁿucⁱⁿt^tio^ern^ruin^ptt^-e^hr^aru^ndp^ltⁱ-ⁿh^ga^rn^od^ul^tiⁱn^neg⁾routine)
(⁽1¹0⁰)^{) Fi}F^rsir^tsⁱⁿt^sin^trs^ut^cr^tu^iocⁿtio^ofnⁱⁿo^tf^erin^rute^ptr^-r^hu^apⁿt^d-h^lina^gnd^roli^un^tg^ineroutine
Figure 4-6. Timing of Interrupt Sequence
Figure. 4-6
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