HD6473258F10V Datasheet, PDF (247/301 Pages) Renesas Technology Corp – Hitachi Single-Chip Microcomputer

Table 15-8. Timing Conditions of On-Chip Supporting Modules (cont.)
Condition A: VCC = 5.0V ±10%, Ø = 0.5 to 10MHz, VSS = 0V,
Ta = –20 to 75˚C (regular specifications), Ta = –40 to 85˚C (wide-range specifications)
Condition B: VCC = 2.7 to 3.6V, VSS = 0V, Ta = –20 to 75˚C, for only H8/3257 and H8/3256
Item
TMR
SCI
Ports
Condition B
Condition A
5MHz
6MHz
8MHz
10MHz
Symbol min max min max min max min max
Timer output tTMOD –
150 –
100 –
100 –
100
delay time
Timer reset
tTMRS 80 –
50 –
50 –
50 –
input setup time
Timer clock
tTMCS 80 –
50 – 50 – 50 –
input setup time
Timer clock
tTMCWH 1.5 –
1.5 – 1.5 – 1.5 –
pulse width
(single edge)
Timer clock
tTMCWL 2.5 –
2.5 – 2.5 – 2.5 –
pulse width
(both edges)
Input (Async) tScyc
2
–
2
–
2
–
2
–
clock (Sync) tScyc
4
–
4
–
4
–
4
–
cycle
Transmit data tTXD –
200 –
100 –
100 –
100
delay time (Sync)
Receive data
tRXS
150 –
100 –
100 –
100 –
setup time (Sync)
Receive data
tRXH 150 –
100 –
100 –
100 –
hold time (Sync)
Input clock
tSCKW 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6
pulse width
Output data
tPWD
–
150 –
100 –
100 –
100
delay time
Input data setup tPRS
80 –
50 –
50 –
50 –
time
Input data hold tPRH
80 –
50 –
50 –
50 –
time
Measurement
Unit conditions
ns Fig. 15-13
ns Fig. 15-15
ns Fig. 15-14
tcyc Fig. 15-14
tcyc Fig. 15-14
tcyc Fig. 15-16
tcyc Fig. 15-16
ns Fig. 15-16
ns Fig. 15-16
ns Fig. 15-16
tScyc Fig. 15-17
ns Fig. 15-18
ns Fig. 15-18
ns Fig. 15-18
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