HD6473258F10V Datasheet, PDF (148/301 Pages) Renesas Technology Corp – Hitachi Single-Chip Microcomputer

ICR upper byte read cycle
T1
T2
T3
Ø
Input at FTI pin
Internal input
capture signal
Figure 7-10. Input Capture Timing (1-State Delay Due to ICR Read)
(2) Input Capture Timing with Noise Canceler: The noise canceler samples the FTI input, and
does generate an internal input capture signal until three to four sampling clock cycles after the rise
or fall of FTI. Figure 7-9 shows the timing.
If the upper byte of the ICR is being read when the internal input capture signal shoul^Fd^igb⁷e^-10
generated, the internal input capture signal is additionally delayed by one system clock cycle (Ø).
FTI
Sampling clock
Noise canceler output
Internal input capture
signal
Figure 7-11. Input Capture Timing with Noise Cancellation
7.4.5 Timing of Input Capture Flag (ICF) Setting
The input capture flag ICF is set to 1 by the internal input capture signal. The FRC contents are
transferred to the ICR at the same time. Figure 7-12 shows the timing of this operation.
Fig 7-11
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