HD6473258F10V Datasheet, PDF (71/301 Pages) Renesas Technology Corp – Hitachi Single-Chip Microcomputer

(1) The value at the mode pins (MD1 and MD0) is latched in bits MDS1 and MDS0 of the mode
control register (MDCR).
(2) In the condition code register (CCR), the I bit is set to 1 to mask interrupts.
(3) The registers of the I/O ports and on-chip supporting modules are initialized.
(4) The CPU loads the program counter with the first word in the vector table (stored at
addresses H’0000 and H’0001) and starts program execution.
The RES pin should be held low when power is switched off, as well as when power is switched
on.
Figure 4-1 indicates the timing of the reset sequence when the vector table and reset routine are
located in on-chip ROM. Figure 4-2 indicates the timing when they are in off-chip memory.
RES
Ø
Internal address
bus
Internal Read
signal
Internal Write
signal
Internal data bus
(16 bits)
Vector
fetch
Internal
Instruction
processing prefetch
(1)
(2)
(2)
(3)
(1) Reset vector address (H'0000)
(2) Starting address of reset routine (contents of H'0000–H'0001)
(3) First instruction of reset routine
Figure 4-1. Reset Sequence (Mode 2 or 3, Reset Routine in On-Chip ROM)
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Figure. 4-1