HD6473258F10V Datasheet, PDF (200/301 Pages) Renesas Technology Corp – Hitachi Single-Chip Microcomputer

Table 9-9. SCI Interrupts
Interrupt
ERI
RXI
TXI
Description
Receive-error interrupt, requested when ORER, FER, or PER
is set. RIE must also be set.
Receive-end interrupt, requested when RDRF and RIE are set.
Transmit-end interrupt, requested when TDRE and TIE are set.
Priority
High
Low
9.5 Application Notes
Application programmers should note the following features of the SCI.
(1) TDR Write: The TDRE bit in the SSR is simply a flag that indicates that the TDR contents
have been transferred to the TSR. The TDR contents can be rewritten regardless of the TDRE
value. If a new byte is written in the TDR while the TDRE bit is 0, before the old TDR contents
have been moved into the TSR, the old byte will be lost. Normally, software should check that the
TDRE bit is set to 1 before writing to the TDR.
(2) Multiple Receive Errors: Table 9-10 lists the values of flag bits in the SSR when multiple
receive errors occur, and indicates whether the RSR contents are transferred to the RDR.
Table 9-10. SSR Bit States and Data Transfer When Multiple Receive Errors Occur
Receive error
Overrun error
Framing error
Parity error
Overrun + framing errors
Overrun + parity errors
Framing + parity errors
Overrun + framing + parity errors
RDRF
1*¹
0
0
1*¹
1*¹
0
1*¹
SSR Bits
ORER
1
0
0
1
1
0
1
FER
0
1
0
1
0
1
1
PER
0
0
1
0
1
1
1
RSR → RDR*²
No
Yes
Yes
No
No
Yes
No
*¹ Set to 1 before the overrun error occurs.
*² Yes: The RSR contents are transferred to the RDR.
No: The RSR contents are not transferred to the RDR.
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