HD6473258F10V Datasheet, PDF (67/301 Pages) Renesas Technology Corp – Hitachi Single-Chip Microcomputer

3.7.2 Access to On-Chip Register Field and External Devices
The on-chip register field (I/O ports, dual-port RAM, on-chip supporting module registers, etc.) and
external devices are accessed in a cycle consisting of three states: T1, T2, and T3. Only one byte of
data can be accessed per cycle, via an 8-bit data bus. Access to word data or instruction codes
requires two consecutive cycles (six states).
Wait States: If requested, additional wait states (TW) are inserted between T2 and T3. The WAIT
pin is sampled at the center of state T2. If it is Low, a wait state is inserted after T2. The WAIT pin
is also sampled at the center of each wait state and if it is still Low, another wait state is inserted.
An external device can have any number of wait states inserted by holding WAIT Low for the
necessary duration.
The bus cycle for the MOVTPE and MOVFPE instructions will be described in section 15,
"E-Clock Interface."
Figure 3-15 shows the access cycle for the on-chip register field. Figure 3-16 shows the associated
pin states. Figures 3-17 (a) and (b) show the read and write access timing for external devices.
Ø
Internal address bus
Internal Read signal
Internal data bus (read)
Internal Write signal
Internal data bus (write)
T1 state
Bus cycle
T2 state
T3 state
Address
Read data
Write data
Figure 3-15. On-Chip Register Field Access Cycle
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