HD6473258F10V Datasheet, PDF (292/301 Pages) Renesas Technology Corp – Hitachi Single-Chip Microcomputer

SSR—Serial Status Register
H’FFDC
SCI0
Bit
7
6
5
4
3
2
1
0
TDRE RDRF ORER FER PER —
—
—
Initial value 1
0
0
0
0
1
1
1
Read/Write R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* —
—
—
Parity Error
0 Cleared by reading PER = 1, then writing 0.
1 Set when a parity error occurs (parity of receive
data does not match parity selected by O/E bit).
Framing Error
0 Cleared by reading FER = 1, then writing 0.
1 Set when a framing error occurs (stop bit is 0).
Overrun Error
0 Cleared by reading ORER = 1, then writing 0.
1 Set when an overrun error occurs (reception of next data is
completed while RDRF bit is set to 1).
Receive Data Register Full
0 Cleared by reading RDRF = 1, then writing 0.
1 Set when one character is received normally and transferred from RSR
to RDR.
Transmit Data Register Empty
0 Cleared by reading TDRE = 1, then writing 0.
1 Set when:
1. Data is transferred from TDR to TSR.
2. TE is cleared while TDRE = 0.
* Software can write a 0 in bits 7 to 3 to clear the flags, but cannot write a 1 in these bits.
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