HD6473258F10V Datasheet, PDF (144/301 Pages) Renesas Technology Corp – Hitachi Single-Chip Microcomputer

(1) Upper byte read
CPU writes
data H’AA
Bus interface
(2) Lower byte read
CPU writes
data H’55
Bus interface
Module data bus
TEMP
[H’55]
FRC H
[H’AA]
FRC L
[H’55]
Module data bus
TEMP
[H’55]
FRC H
[]
FRC L
[]
Figure 7-3 (b). Read Access to FRC (When FRC Contains H’AA55)
7.4 Operation
7.4.1 FRC Incrementation Timing
The FRC increments on a pulse generated once for each cycle of the selected (internal or external)
clock source.
(1) Internal Clock Sources: Can be selected by the CKS1 and CKS0 bits in the TCR. Inte^Fr^igna⁷l^{-3 (b)}
clock sources are created by dividing the system clock (Ø). Three internal clock sources are
available: Ø/2, Ø/8, and Ø/32. Figure 7-4 shows the increment timing.
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