PD178004A_15 Datasheet, PDF (40/58 Pages) Renesas Technology Corp – PD178004A_15

µPD178004A, 178006A, 178016A, 178018A
(vii) I²C Bus mode (SCL ... internal clock output)
Parameter
Symbol
Test Conditions
MIN.
TYP.
SCL cycle time
SCL high-level width
tKCY7
tKH7
R = 1 kΩ
C = 100 pF ^Note
10
tKCY7 – 160
SCL low-level width
tKL7
tKCY7 – 50
SDA0, SDA1 setup time (to SCL↑) tSIK7
200
SDA0, SDA1 hold time
tKSI7
0
(from SCL↓)
SDA0, SDA1 output delay time
(from SCL↓)
tKSO7
4.5 V ≤ VDD ≤ 5.5 V
0
3.5 V ≤ VDD < 4.5 V
0
SDA0, SDA1↓ from SCL↑ or
tKSB
200
SDA0, SDA1↑ from SCL↑
SCL↓ from SDA0, SDA1↓
tSBK
400
SDA0, SDA1 high-level width
tSBH
500
MAX.
300
500
Unit
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note R and C are the load resistance and load capacitance of SCL, SDA0 and SDA1 output line.
(viii) I²C Bus mode (SCL ... external clock input)
Parameter
Symbol
Test Conditions
MIN.
SCL cycle time
tKCY8
1 000
SCL high-/low-level width
tKH8, tKL8
400
SDA0, SDA1 setup time (to SCL↑) tSIK8
SDA0, SDA1 hold time
tKSI8
0
(from SCL↓)
SDA0, SDA1 output delay time
from SCL↓
tKSO8
R = 1 kΩ
4.5 V ≤ VDD ≤ 5.5 V
0
C = 100 pF ^Note _{3.5 V ≤ VDD < 4.5 V}
0
SDA0, SDA1↓ from SCL↑ or
tKSB
200
SDA0, SDA1↑ from SCL↑
SCL↓ from SDA0, SDA1↓
tSBK
400
SDA0, SDA1 high-level width
tSBH
500
SCL at rising or falling edge time tR8, tF8
TYP. MAX.
200
300
500
1 000
Note R and C are the load resistance and load capacitance of SDA0 and SDA1 output line.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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