PD178004A_15 Datasheet, PDF (10/58 Pages) Renesas Technology Corp – PD178004A_15

2. BLOCK DIAGRAM
µPD178004A, 178006A, 178016A, 178018A
TI1/P33
TI2/P34
8-bit TIMER/
EVENT COUNTER 1
8-bit TIMER/
EVENT COUNTER 2
8-bit TIMER 3
WATCHDOG TIMER
BASIC TIMER
SI0/SB0/SDA0/P25
SO0/SB1/SDA1/P26
SCK0/SCL/P27
SI1/P20
SO1/P21
SCK1/P22
STB/P23
BUSY/P24
SERIAL
INTERFACE 0
SERIAL
INTERFACE 1
ANI0/P10 to
ANI5/P15
6
A/D CONVERTER
INTP0/P00 to
INTP6/P06
7
INTERRUPT
CONTROL
BEEP/P36
RESET
X1
X2
VDDPORT
GNDPORT
VDD
BUZZER OUTPUT
SYSTEM
CONTROL
78K/0
CPU
CORE
ROM
RAM
RESET
CPU
PERIPHERAL
REGOSC
REGCPU
GND
VOLTAGE
REGULATOR
VOSC
VCPU
PORT 0
PORT 1
P00
6 P01 to P06
6 P10 to P15
PORT 2
8 P20 to P27
PORT 3
8 P30 to P37
PORT 4
8 P40 to P47
PORT 5
8 P50 to P57
PORT 6
8 P60 to P67
PORT 12
6 P120 to P125
PORT 13 ³ P132 to P134
D/A CONVERTER
(PWM)
3
PWM0/P132 to
PWM2/P134
FREQUENCY
COUNTER
AMIFC
FMIFC
PLL
PLL
VOLTAGE
REGULATOR
EO0
EO1
VCOL
VCOH
VDDPLL
GNDPLL
IC
Remark The internal ROM and RAM capacities depend on the version.
8