PD178004A_15 Datasheet, PDF (39/58 Pages) Renesas Technology Corp – PD178004A_15

µPD178004A, 178006A, 178016A, 178018A
(v) 2-wire serial I/O mode (SCK0 ... internal clock output)
Parameter
Symbol
Test Conditions
MIN.
TYP. MAX.
Unit
SCK0 cycle time
tKCY5
R = 1 kΩ
1 600
ns
SCK0 high-level width
tKH5
C = 100 pF ^Note
tKCY5/2 – 160
ns
SCK0 low-level width
tKL5
4.5 V ≤ VDD ≤ 5.5 V tKCY5/2 – 50
ns
3.5 V ≤ VDD < 4.5 V tKCY5/2 – 100
ns
SB0, SB1 setup time (to SCK0↑) tSIK5
4.5 V ≤ VDD ≤ 5.5 V 300
ns
3.5 V ≤ VDD < 4.5 V 350
ns
400
ns
SB0, SB1 hold time (from SCK0↑) tKSI5
600
ns
SB0, SB1 output delay time from
SCK0↓
tKSO5
0
300
ns
Note R and C are the load resistance and load capacitance of SCK0, SB0 and SB1 output line.
(vi) 2-wire serial I/O mode (SCK0 ... external clock input)
Parameter
Symbol
Test Conditions
MIN.
TYP. MAX.
Unit
SCK0 cycle time
tKCY6
1 600
ns
SCK0 high-level width
tKH6
650
ns
SCK0 low-level width
SB0, SB1 setup time (to SCK0↑)
SB0, SB1 hold time (from SCK0↑)
SB0, SB1 output delay time from
SCK0↓
tKL6
tSIK6
tKSI6
tKSO6
800
100
tKCY6/2
R = 1 kΩ
4.5 V ≤ VDD ≤ 5.5 V
0
C = 100 pF ^Note _{3.5 V ≤ VDD < 4.5 V}
0
ns
ns
ns
300
ns
500
ns
SCK0 at rising or falling edge time tR6, tF6
1 000
ns
Note R and C are the load resistance and load capacitance of SB0 and SB1 output line.
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