PD178004A_15 Datasheet, PDF (18/58 Pages) Renesas Technology Corp – PD178004A_15

µPD178004A, 178006A, 178016A, 178018A
5.2 CLOCK GENERATOR
The instruction execution time can be changed as follows.
0.44 µs/0.88 µs/1.78 µs/3.56 µs/7.11 µs/14.22 µs (@ 4.5-MHz crystal oscillator with system clock.)
Figure 5-1. Clock Generator Block Diagram
Prescaler
Clock to the PLL
frequency synthesizer,
basic timer and buzzer
output control circuit.
X1
System fX
Clock to peripheral
Clock
X2
Oscillator
Selector
fXX
Prescaler
hardware other than
the above.
Scaler
fXX fXX fXX fXX
2 2² 2³ 2⁴
fX
STOP
2
Selector
Standby
Control
Circuit
Wait Control
Circuit
CPU Clock
(fCPU)
To INTP0
Sampling Clock
5.3 TIMER
The µPD178004A, 178006A, 178016A, and 178018A incorporate 5 channels of the timer.
• Basic timer
: 1 channel
• 8-bit timer/event counter
: 2 channels
• 8-bit timer (D/A converter) ^Note
: 1 channel
• Watchdog timer
: 1 channel
Note Used is shared with the 8/9-bit resolution × 3-channel D/A converter (PWM output).
Figure 5-2. Basic Timer Block Diagram
4.5 MHz
Divider
INTTMC
16