PD178004A_15 Datasheet, PDF (38/58 Pages) Renesas Technology Corp – PD178004A_15

µPD178004A, 178006A, 178016A, 178018A
(iii) SBI mode (SCK0 ... internal clock output)
Parameter
Symbol
Test Conditions
MIN.
TYP. MAX.
Unit
SCK0 cycle time
tKCY3
4.5 V ≤ VDD ≤ 5.5 V
800
ns
3.5 V ≤ VDD < 4.5 V
3 200
ns
SCK0 high-/low-level width
tKH3,
4.5 V ≤ VDD ≤ 5.5 V
tKCY3/2 – 50
ns
tKL3
3.5 V ≤ VDD < 4.5 V
tKCY3/2 – 150
ns
SB0, SB1 setup time (to SCK0↑)
tSIK3
4.5 V ≤ VDD ≤ 5.5 V
100
ns
3.5 V ≤ VDD < 4.5 V
300
ns
SB0, SB1 hold time (from SCK0↑) tKSI3
tKCY3/2
ns
SB0, SB1 output delay time from
SCK0↓
SB0, SB1↓ from SCK0↑
SCK0↓ from SB0, SB1↓
tKSO3
tKSB
tSBK
R = 1 kΩ
4.5 V ≤ VDD ≤ 5.5 V
C = 100 pF ^Note _{3.5 V ≤ VDD < 4.5 V}
0
0
tKCY3
tKCY3
250
ns
1 000
ns
ns
ns
SB0, SB1 high-level width
tSBH
tKCY3
ns
SB0, SB1 low-level width
tSBL
tKCY3
ns
Note R and C are the load resistance and load capacitance of SB0 and SB1 output line.
(iv) SBI mode (SCK0 ... external clock input)
Parameter
Symbol
Test Conditions
MIN.
TYP. MAX.
Unit
SCK0 cycle time
tKCY4
4.5 V ≤ VDD ≤ 5.5 V
800
ns
3.5 V ≤ VDD < 4.5 V
3 200
ns
SCK0 high-/low-level width
tKH4,
4.5 V ≤ VDD ≤ 5.5 V
400
ns
tKL4
3.5 V ≤ VDD < 4.5 V
1 600
ns
SB0, SB1 setup time (to SCK0↑)
tSIK4
4.5 V ≤ VDD ≤ 5.5 V
100
ns
3.5 V ≤ VDD < 4.5 V
300
ns
SB0, SB1 hold time (from SCK0↑) tKSI4
tKCY4/2
ns
SB0, SB1 output delay time from tKSO4 R = 1 kΩ
4.5 V ≤ VDD ≤ 5.5 V
0
SCK0↓
C = 100 pF ^Note _{3.5 V ≤ VDD < 4.5 V}
0
300
ns
1 000
ns
SB0, SB1↓ from SCK0↑
tKSB
tKCY4
ns
SCK0↓ from SB0, SB1↓
tSBK
tKCY4
ns
SB0, SB1 high-level width
tSBH
tKCY4
ns
SB0, SB1 low-level width
tSBL
tKCY4
ns
SCK0 at rising or falling edge time tR4, tF4
1 000
ns
Note R and C are the load resistance and load capacitance of SB0 and SB1 output line.
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