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| R01AN1504EJ0100 Datasheet, PDF (36/50 Pages) Renesas Technology Corp – Using the DTC to Perform Continuous Clock | |||
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RL78/G14
4.8.12 DTC Initialization
Figure 4.16 shows the DTC initialization.
Using the DTC to Perform Continuous Clock
Synchronous Serial Communication
R_DTC_Create
Supply an input clock to the DTC
Disable to active the DTC
Set the DTC base address
PER1 register
DTCEN bit â 1: Enables input clock supply
DTCEN0 register â 00H
DTCEN1 register â 00H
DTCEN2 register â 00H
DTCEN3 register â 00H
DTCEN4 register â 00H
DTCBAR register â FDH
Set the start address of
the DTC control data to
the DTC vector table
Set DTCD0
Set DTCD1
return
Figure 4.16 DTC Initialization
DTCCR0 register â 18H
SZ bit = 0: Transfer byte size: 8-bit
CHNE bit = 1: Chain transfers enabled
DAMOD bit = 1: Transfer destination address incremented
SAMOD bit = 0: Transfer source address fixed
MODE bit = 0: Normal mode
DTBLS0 register â 01H: Block size of the data to be transferred
by one activation: 1 byte
DTCCT0 register â 07H: Number of DTC data transfers: 7
DTRLD0 register â 07H: Transfer count in repeat mode: 7
DTSAR0 register â FF10H: Specify the transfer source address to FF10H
DTDAR0 register â E900H: Specify the transfer destination address to E900H
DTCCR1 register â 04H
SZ bit = 0: Transfer byte size: 8-bit
CHNE bit = 0: Chain transfers disabled
DAMOD bit = 0: Transfer destination address fixed
SAMOD bit = 1: Transfer source address incremented
MODE bit = 0: Normal mode
DTBLS1 register â 01H: Block size of the data to be transferred
by one activation: 1 byte
DTCCT1 register â 07H: Number of DTC data transfers: 7
DTSAR1 register â E911H: Specify the transfer source address to E911H
DTDAR1 register â FF10H: Specify the transfer destination address to FF10H
R01AN1504EJ0100 Rev. 1.00
Feb. 14, 2014
Page 36 of 47
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