R01AN1504EJ0100 Datasheet, PDF (22/50 Pages) Renesas Technology Corp – Using the DTC to Perform Continuous Clock

RL78/G14
Clearing the CSI00 error flag
• Serial flag clear trigger register (SIR00)
Using the DTC to Perform Continuous Clock
Synchronous Serial Communication
Symbol
SIR00
Value
15 14 13 12 11 10 9 8 7 6 5 4 3
2
1
0
0
0
0
0
0
0 0 0 0 0 0 0 0 FECT00 PECT00 OVCT00
‒ ‒ ‒ ‒ ‒ ‒ ‒‒‒‒‒‒‒
1
1
1
• Bit 2
FECT00
bit
0
1
Clear trigger of framing error of channel 0
Not cleared
Clears the FEF00 bit of the SSR00 register to 0
• Bit 1
PECT00
bit
0
1
Clear trigger of parity error of channel 0
Not cleared
Clears the PEF00 bit of the SSR00 register to 0
• Bit 0
OVCT00
bit
0
1
Clear trigger of overrun error of channel 0
Not cleared
Clears the OVF00 bit of the SSR00 register to 0
For details on register setting, refer to the RL78/G14 User’s Manual: Hardware.
Legend symbol:
×: Unused bit; blank cell: unchanged bit; ‒: reserved bit or unallocated bit
R01AN1504EJ0100 Rev. 1.00
Feb. 14, 2014
Page 22 of 47