R01AN1504EJ0100 Datasheet, PDF (34/50 Pages) Renesas Technology Corp – Using the DTC to Perform Continuous Clock

RL78/G14
Using the DTC to Perform Continuous Clock
Synchronous Serial Communication
Retrieving the overrun error detection flag status
• Serial status register 00 (SSR00)
Symbol 15 14 13 12 11 10 9 8 7 6
5 43 2
1
0
SSR00 0 0 0 0 0 0 0 0 0 TSF BFF 0 0 FEC PEC OVC
00 00
00 00 00
• Bit 0
OVC00
bit
0
1
No error occurs
An error occurs
Overrun error detection flag of channel 0
Setting the clear trigger of the overrun error flag
• Serial flag clear trigger register (SIR00)
Clears an overrun error flag when an overrun error occurs.
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3
2
1
0
SIR00 0 0 0 0 0 0 0 0 0 0 0 0 0 FECT00 PECT00 OVCT00
Value ‒ ‒ ‒ ‒ ‒ ‒ ‒ ‒ ‒ ‒ ‒ ‒ ‒
×
×
1
• Bit 0
OVCT00
bit
0
1
Clear trigger of overrun error flag of channel 0
Not cleared
Clears the OVF00 bit of the SSR00 register to 0
Storing the receive data
• CSI00 data register 00 (SIO00)
Reads the receive data
Symbol
7
6
5
4
3
2
1
0
SIO00
‒
‒
‒
‒
‒
‒
‒
‒
For details on register setting, refer to the RL78/G14 User’s Manual: Hardware.
Legend symbol:
×: Unused bit; blank cell: unchanged bit; ‒: reserved bit or unallocated bit
R01AN1504EJ0100 Rev. 1.00
Feb. 14, 2014
Page 34 of 47