R01AN1504EJ0100 Datasheet, PDF (23/50 Pages) Renesas Technology Corp – Using the DTC to Perform Continuous Clock

RL78/G14
Setting the CSI00 operating mode
• Serial mode register 00 (SMR00)
Operating clock (fMCK): CK00
Transfer clock (fTCLK): Divided fMCK
Operating mode: CSI mode
Using the DTC to Perform Continuous Clock
Synchronous Serial Communication
Symbol 15 14 13 12 11 10 9 8
7
6 543 2
1
0
SMR00 CKS CCS 0 0 0 0 0 STS 0 SIS 1 0 0 MD MD MD
00 00
00
000
002 001 000
Value 0
0 ‒ ‒ ‒ ‒‒ 0
‒ 0 1‒‒ 0
0
0
• Bit 15
CKS00
bit
Selection of operating clock (fMCK) of channel 0
0
Operating clock CK00 set by the SPS0 register
1
Operating clock CK01 set by the SPS0 register
Operating clock (fMCK) is used by the edge detector. In addition, depending on the setting of the
CCS00 bit and the higher 7 bits of the SDR00 register, a transfer clock (fTCLK) is generated.
• Bit 14
CCS00
bit
Selection of transfer clock (fTCLK) of channel 0
0
Divided operating clock f_{M_C__K__}s_{__}p_{__}e_{__}cified by the CKS00 bit
1
Clock input fSCK from the SCK00 pin (slave transfer in CSI mode)
Transfer clock fTCLK is used for the shift register, communication controller, output controller,
interrupt controller, and error controller. When CCS00 = 0, the division ratio of operating clock
(fMCK) is set by the higher 7 bits of the SDR00 register.
• Bits 2 and 1
MD002 MD001
bit
bit
Setting of operating mode of channel 0
0
0 CSI mode
0
1 UART mode
1
0
Simplified I²C mode
1
1 Setting prohibited
• Bit 0
MD000
bit
0
1
Selection of interrupt source of channel 0
Transfer end interrupt
Buffer empty interrupt
(Occurs when data is transferred from the SDR00 register to the shift register)
For details on register setting, refer to the RL78/G14 User’s Manual: Hardware.
Legend symbol:
×: Unused bit; blank cell: unchanged bit; ‒: reserved bit or unallocated bit
R01AN1504EJ0100 Rev. 1.00
Feb. 14, 2014
Page 23 of 47