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HYB18T512400B2C Datasheet, PDF (55/69 Pages) Qimonda AG – 512-Mbit Double-Data-Rate-Two SDRAM
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Internet Data Sheet
HY[B/I]18T512[40/80/16]0B2[C/F](L)
512-Mbit Double-Data-Rate-Two SDRAM
Parameter
Symbol
DDR2–400
Min.
Max.
Unit
Note1)2)3)4)5)
6)
Clock half period
Data-out high-impedance time from CK / CK
Address and control input hold time
Address and control input pulse width
(each input)
Address and control input setup time
DQ low-impedance time from CK / CK
DQS low-impedance from CK / CK
Mode register set command cycle time
OCD drive mode output delay
Data output hold time from DQS
Data hold skew factor
Average periodic refresh Interval
Average periodic refresh Interval
Auto-Refresh to Active/Auto-Refresh
command period
tHP
tHZ
tIH(base)
tIPW
tIS(base)
tLZ(DQ)
tLZ(DQS)
tMRD
tOIT
tQH
tQHS
tREFI
tREFI
MIN. (tCL, tCH)
—
475
0.6
350
2 × tAC.MIN
tAC.MIN
2
0
tHP –tQHS
—
—
—
105
tAC.MAX
—
—
—
tAC.MAX
tAC.MAX
—
12
—
450
7.8
3.9
—
11)
ps
12)
ps
10)
tCK
ps
10)
ps
13)
ps
13)
tCK
ns
ps
µs
13)14)
µs
15)17)
ns
16)
Precharge-All (4 banks) command period
Read preamble
Read postamble
Active bank A to Active bank B command
period
Active bank A to Active bank B command
period
tRP
tRPRE
tRPST
tRRD
tRRD
tRP
0.9
0.40
7.5
10
—
1.1
0.60
—
—
ns
tCK
13)
tCK
13)
ns
13)17)
ns
15)21)
Internal Read to Precharge command delay
Write preamble
Write postamble
Write recovery time for write without Auto-
Precharge
Internal Write to Read command delay
Exit power down to any valid command
(other than NOP or Deselect)
Exit active power-down mode to Read
command (slow exit, lower power)
tRTP
tWPRE
tWPST
tWR
tWTR
tXARD
tXARDS
7.5
0.25
0.40
15
10
2
6 – AL
—
—
0.60
—
—
—
—
ns
tCK
tCK
18)
ns
ns
19)
tCK
20)
tCK
20)
Exit precharge power-down to any valid
tXP
2
command (other than NOP or Deselect)
—
tCK
Exit Self-Refresh to non-Read command
tXSNR
tRFC +10
—
ns
Exit Self-Refresh to Read command
tXSRD
200
—
Write recovery time for write with Auto-
WR
tWR/tCK
—
Precharge
tCK
tCK
21)
1) VDDQ = 1.8 V ± 0.1 V; VDD = 1.8 V ±0.1 V.
2) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down
and then restarted through the specified initialization sequence before normal operation can continue.
Rev. 1.12, 2007-05
55
10062006-YPTZ-CDR7
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