HYB18T512400B2C Datasheet, PDF(17/69 Page) Qimonda AG – 512-Mbit Double-Data-Rate-Two SDRAM

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HYB18T512400B2C Datasheet, PDF (17/69 Pages) Qimonda AG – 512-Mbit Double-Data-Rate-Two SDRAM

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Internet Data Sheet

HY[B/I]18T512[40/80/16]0B2[C/F](L)

512-Mbit Double-Data-Rate-Two SDRAM

FIGURE 3

Chip Configuration for Ã16 components, PG-TFBGA-84 (top view)

6''

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66 6

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6664

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6'' 4

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03 37

Notes

1. UDQS/UDQS is data strobe for DQ[15:8], LDQS/LDQS is

data strobe for DQ[7:0]

2. LDM is the data mask signal for DQ[7:0], UDM is the data

mask signal for DQ[15:8]

3. VDDL and VSSDL are power and ground for the DLL. VDDL is

connected to VDD on the device. VDD, VDDQ, VSSDL, VSS,

and VSSQ are isolated on the device.

Rev. 1.12, 2007-05

17

10062006-YPTZ-CDR7

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