HYB18T512400B2C Datasheet, PDF (10/69 Pages) Qimonda AG – 512-Mbit Double-Data-Rate-Two SDRAM

Internet Data Sheet
HY[B/I]18T512[40/80/16]0B2[C/F](L)
512-Mbit Double-Data-Rate-Two SDRAM
2
Configuration
This chapter contains the Chip Configuration.
2.1
Chip Configuration
The chip configuration of a DDR2 SDRAM is listed by function in Table 7. The abbreviations used in the Ball# and Buffer Type
columns are explained in Table 8 and Table 9 respectively. The ball numbering for the FBGA package is depicted in Figure 1
for ×4, Figure 2 for ×8 and Figure 3 for ×16.
Ball#
Name
Ball
Type
Clock Signals ×4/×8 organization
E8
CK
I
F8
CK
I
F2
CKE
I
Clock Signals ×16 organization
J8
CK
I
K8
CK
I
K2
CKE
I
Buffer
Type
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Control Signals ×4/×8 organizations
F7
RAS
I
SSTL
G7
CAS
I
SSTL
F3
WE
I
SSTL
G8
CS
I
SSTL
Control Signals ×16 organization
K7
RAS
I
SSTL
L7
CAS
I
SSTL
K3
WE
I
SSTL
L8
CS
I
SSTL
Address Signals ×4/×8 organizations
G2
BA0
I
SSTL
G3
BA1
I
SSTL
Function
TABLE 7
Chip Configuration of DDR2 SDRAM
Clock Signal CK, Complementary Clock Signal CK
Clock Enable
Clock Signal CK, Complementary Clock Signal CK
Note: See functional description in x4/x8 organization
Clock Enable
Note: See functional description in x4/x8 organization
Row Address Strobe (RAS), Column Address Strobe (CAS), Write
Enable (WE)
Chip Select
Row Address Strobe (RAS), Column Address Strobe (CAS), Write
Enable (WE)
Chip Select
Bank Address Bus 1:0
Rev. 1.12, 2007-05
10
10062006-YPTZ-CDR7