HYB18T512400B2C Datasheet, PDF (33/69 Pages) Qimonda AG – 512-Mbit Double-Data-Rate-Two SDRAM

Internet Data Sheet
HY[B/I]18T512[40/80/16]0B2[C/F](L)
512-Mbit Double-Data-Rate-Two SDRAM
5.4
Output Buffer Characteristics
This chapter describes the Output Buffer Characteristics.
TABLE 29
SSTL_18 Output DC Current Drive
Symbol
Parameter
SSTL_18
Unit
Note
I_OH
Output Minimum Source DC Current
–13.4
mA
1)2)
I_OL
Output Minimum Sink DC Current
13.4
mA
2)3)
1) V_DDQ = 1.7 V; V_OUT = 1.42 V. (V_OUT–V_DDQ) / I_OH must be less than 21 Ohm for values of V_OUT between V_DDQ and V_DDQ – 280 mV.
2) The values of I_OH(dc) and I_OL(dc) are based on the conditions given in ¹⁾ and ³⁾. They are used to test drive current capability to ensure V_IH.MIN.
plus a noise margin and V_IL.MAX minus a noise margin are delivered to an SSTL_18 receiver. The actual current values are derived by
shifting the desired driver operating points along 21 Ohm load line to define a convenient current for measurement.
3) V_DDQ = 1.7 V; V_OUT = 280 mV. V_OUT / I_OL must be less than 21 Ohm for values of V_OUT between 0 V and 280 mV.
TABLE 30
SSTL_18 Output AC Test Conditions
Symbol Parameter
SSTL_18
Unit
Note
V_OH
Minimum Required Output Pull-up
V_TT + 0.603
V
1)
V_OL
Maximum Required Output Pull-down
V_TT – 0.603
V
1)
V_OTR
Output Timing Measurement Reference Level
0.5 × V_DDQ
V
1) SSTL_18 test load for V_OH and V_OL is different from the referenced load. The SSTL_18 test load has a 20 Ohm series resistor additionally
to the 25 Ohm termination resistor into V_TT. The SSTL_18 definition assumes that ± 335 mV must be developed across the effectively
25 Ohm termination resistor (13.4 mA × 25 Ohm = 335 mV). With an additional series resistor of 20 Ohm this translates into a minimum
requirement of 603 mV swing relative to V_TT, at the ouput device (13.4 mA × 45 Ohm = 603 mV).
TABLE 31
OCD Default Characteristics
Symbol
Description
Min.
Nominal Max.
Unit
Note
—
Output Impedance
—
Ω
1)2)
—
Pull-up / Pull down mismatch
0
—
4
Ω
1)2)3)
—
Output Impedance step size
for OCD calibration
0
—
1.5
Ω
4)
S_OUT
Output Slew Rate
1.5
—
5.0
V / ns
1)5)6)7)
1) V_DDQ = 1.8 V ± 0.1 V; V_DD = 1.8 V ± 0.1 V
2) Impedance measurement condition for output source dc current: V_DDQ = 1.7 V, V_OUT = 1420 mV; (V_OUT–V_DDQ) / I_OH must be less than
23.4 Ohms for values of V_OUT between V_DDQ and V_DDQ – 280 mV. Impedance measurement condition for output sink dc current: V_DDQ =
1.7 V; V_OUT = –280 mV; V_OUT / I_OL must be less than 23.4 Ohms for values of V_OUT between 0 V and 280 mV.
3) Mismatch is absolute value between pull-up and pull-down, both measured at same temperature and voltage.
4) This represents the step size when the OCD is near 18 Ohms at nominal conditions across all process parameters and represents only
the DRAM uncertainty. A 0 Ohm value (no calibration) can only be achieved if the OCD impedance is 18 ± 0.75 Ohms under nominal
conditions.
5) The absolute value of the Slew Rate as measured from DC to DC is equal to or greater than the Slew Rate as measured from AC to AC.
This is verified by design and characterization but not subject to production test.
6) Timing skew due to DRAM output Slew Rate mis-match between DQS / DQS and associated DQ’s is included in t_DQSQ and t_QHS
specification.
7) DRAM output Slew Rate specification applies to 400, 533 and 667 MT/s speed bins.
Rev. 1.12, 2007-05
33
10062006-YPTZ-CDR7