HYB18T512400B2C Datasheet, PDF (19/69 Pages) Qimonda AG – 512-Mbit Double-Data-Rate-Two SDRAM

Internet Data Sheet
HY[B/I]18T512[40/80/16]0B2[C/F](L)
512-Mbit Double-Data-Rate-Two SDRAM
3
Functional Description
This chapter contains the functional description.
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Field Bits Type¹⁾
BA2 16 reg. addr.
BA1 15
BA0 14
A13 13
PD
12 w
WR [11:9] w
DLL 8
w
TM
7
w
TABLE 11
Mode Register Definition (BA[2:0] = 000B)
Description
Bank Address [2]
Note: BA2 not available on 256 Mbit and 512 Mbit components
0_B BA2 Bank Address
Bank Address [1]
0_B BA1 Bank Address
Bank Address [0]
0_B BA0 Bank Address
Address Bus[13]
Note: A13 is not available for 256 Mbit and x16 512 Mbit configuration
0_B A13 Address bit 13
Active Power-Down Mode Select
0_B PD Fast exit
1_B PD Slow exit
Write Recovery²⁾
Note: All other bit combinations are illegal.
001_B WR 2
010_B WR 3
011_B WR 4
100_B WR 5
101_B WR 6
DLL Reset
0_B DLL No
1_B DLL Yes
Test Mode
0_B TM Normal Mode
1_B TM Vendor specific test mode
Rev. 1.12, 2007-05
19
10062006-YPTZ-CDR7