 English |
|
|
|
|
|
|
|
| HYB18T512400B2C Datasheet, PDF (21/69 Pages) Qimonda AG – 512-Mbit Double-Data-Rate-Two SDRAM | |||
| |||
| ◁ |
Internet Data Sheet
HY[B/I]18T512[40/80/16]0B2[C/F](L)
512-Mbit Double-Data-Rate-Two SDRAM
Field
RDQS
Bits Type1)
11 w
DQS 10 w
OCD [9:7] w
Program
AL
[5:3] w
RTT
6,2 w
DIC
1
w
DLL
0
w
1) w = write only register bits
Description
Read Data Strobe Output (RDQS, RDQS)
0B RDQS Disable
1B RDQS Enable
Complement Data Strobe (DQS Output)
0B DQS Enable
1B DQS Disable
Off-Chip Driver Calibration Program
000B OCD OCD calibration mode exit, maintain setting
001B OCD Drive (1)
010B OCD Drive (0)
100B OCD Adjust mode
111B OCD OCD calibration default
Additive Latency
Note: All other bit combinations are illegal.
000B AL 0
001B AL 1
010B AL 2
011B AL 3
100B AL 4
101B AL 5
110B AL 6
Nominal Termination Resistance of ODT
Note: See Table 23 âODT DC Electrical Characteristicsâ on Page 29
00B RTT â (ODT disabled)
01B RTT 75 Ohm
10B RTT 150 Ohm
11B RTT 50 Ohm
Off-chip Driver Impedance Control
0B DIC Full (Driver Size = 100%)
1B DIC Reduced
DLL Enable
0B DLL Enable
1B DLL Disable
Rev. 1.12, 2007-05
21
10062006-YPTZ-CDR7
|
▷ |
German
Russian
Spanish
Italian
Polish
Chinese
Japanese
Korean
French
Portuguese