HYB18T512400B2C Datasheet, PDF (30/69 Pages) Qimonda AG – 512-Mbit Double-Data-Rate-Two SDRAM

Internet Data Sheet
HY[B/I]18T512[40/80/16]0B2[C/F](L)
512-Mbit Double-Data-Rate-Two SDRAM
5.3
DC & AC Characteristics
DDR2 SDRAM pin timing are specified for either single ended
or differential mode depending on the setting of the EMRS(1)
“Enable DQS” mode bit; timing advantages of differential
mode are realized in system design. The method by which the
DDR2 SDRAM pin timing are measured is mode dependent.
In single ended mode, timing relationships are measured
relative to the rising or falling edges of DQS crossing at V_REF.
In differential mode, these timing relationships are measured
relative to the crosspoint of DQS and its complement, DQS.
This distinction in timing methods is verified by design and
characterization but not subject to production test. In single
ended mode, the DQS (and RDQS) signals are internally
disabled and don’t care.
Symbol
V_IH(dc)
V_IL(dc)
V_IH(ac)
V_IL(ac)
Parameter
DC input logic high
DC input low
AC input logic high
AC input low
TABLE 25
DC & AC Logic Input Levels for DDR2-667 and DDR2-800
DDR2-667, DDR2-800
Units
Min.
Max.
V_REF + 0.125
V_DDQ + 0.3
V
–0.3
V_REF – 0.125
V
V_REF + 0.200
—
V
—
V_REF – 0.200
V
Symbol
V_IH(dc)
V_IL(dc)
V_IH(ac)
V_IL(ac)
Parameter
DC input logic high
DC input low
AC input logic high
AC input low
TABLE 26
DC & AC Logic Input Levels for DDR2-533 and DDR2-400
DDR2-533, DDR2-400
Units
Min.
Max.
V_REF + 0.125
V_DDQ + 0.3
V
–0.3
V_REF - 0.125
V
V_REF + 0.250
—
V
—
V_REF - 0.250
V
Rev. 1.12, 2007-05
30
10062006-YPTZ-CDR7