UMA1002 Datasheet, PDF (9/36 Pages) NXP Semiconductors – Data processor for cellular radio DPROC2

Philips Semiconductors
Data processor for cellular radio
(DPROC2)
Product specification
UMA1002
I²C-bus serial data link (SDA; SCL)
SDA is the bidirectional data line, SCL is the clock input
from an I²C-bus master. These constitute a typical I²C link
and conform to standard I²C-bus characteristics.
A detailed description of the I²C-bus specification, with
applications, is given in the brochure “The I²C-bus and
how to use it”. This brochure may be ordered using the
code 9398 393 40011.
• Data rate up to 100 kbits/s.
I²C-BUS REGISTERS
The I²C-bus register block resides internally within the
I²C-bus interface block and contains various items of
status and control information which are transferred to and
from DPROC2 via the I²C-bus. The block is organized into
three 8-bit registers:
• Status register which contains read only items
• Control registers 1 and 2 which contain write only items.
SLAVE ADDRESS SELECT (A0)
Selection of the device slave address is achieved by
connecting A0 to either V_SS or V_DDD. The slave address is
defined in accordance with the I²C-bus specifications as
shown in Fig.4.
handbook, halfpage
1 1 0 1 1 X⁽¹⁾ A0 R/W
MBD831
(1) X = don’t care.
Fig.4 Device slave address.
Table 3 I²C-bus register map
REGISTER
Status (read)
Control 1 (write)
Control 2 (write)
7
−
BUFEN
MAJ
6
−
SERV
MR1
5
WSYNC
STS
MR0
BIT
4
BUSY
TXRST
DBCH
3
TXABRT
ABREN
DCFM
2
TXIP
FVC
ENSM
1
MSCC1
STEN
ESCC1
0
MSCC0
SATEN
ESCC0
1997 Jan 28
9