UMA1002 Datasheet, PDF (19/36 Pages) NXP Semiconductors – Data processor for cellular radio DPROC2

Philips Semiconductors
Data processor for cellular radio
(DPROC2)
Product specification
UMA1002
BCH AND MANCHESTER ENCODING BLOCK
The functions performed by this circuit block include:
• Reception of data from the System Controller
• Parity generation
• Message construction
• Manchester encoding.
Each 36-bit Information Word sent on the Reverse Voice
and Control Channels is coded into a 48-bit code word.
The code word consists of the 36-bit word followed by
12 parity bits. These parity bits are formed by clocking the
information word into a 12-bit feedback shift register with
characteristic polynomial:
1 + x³ + x⁴ + x⁵ + x⁸ + x¹⁰ + x¹²
The BCH Encoder Block constructs the Reverse Voice
and Control Channel data streams from the information it
receives from the System Controller.
The streams are formed out of the four possible field types:
• Dotting (data inversions)
• 11-bit Synchronization Word
• Digital Colour Code (see Table 11)
• 48-bit code word.
The 2 bits of DCC received from the System Controller are
coded into a 7-bit word as shown in Table 11.
The data sense for Manchester Encoding has a NRZ
logic 1 encoded as a 0-to-1 transition and a NRZ logic 0
encoded as a 1-to-0 transition.
REVERSE CONTROL CHANNEL ACCESS ARBITRATION
The AMPS and TACS specifications require a method of
arbitration on the Reverse Control Channel to prevent two
mobiles from transmitting on the same channel at the
same time.
This function is performed by DPROC2 monitoring the
Busy/Idle stream sent on the Forward Control Channel.
The AMPS and TACS specifications state that once the
mobile has commenced transmitting on the Reverse
Control Channel it must monitor the Busy/Idle stream.
If this stream becomes active outside a predetermined
‘window’, measured from the start of the transmission of
the message, the mobile must terminate its transmission
and disable the transmitter immediately.
In the Cellular Radio chip-set there are two levels of control
of the RF transmitter; the first is absolute control by the
System Controller, the second is conditional by other
devices in the set. In DPROC2 the conditional control of
the transmitter is performed via the output TXCTRL.
This line is effectively wired ORed together, using
open-drain outputs, with other devices which may wish to
control the transmitter. When these devices do not wish to
disable the transmitter their output is in a HIGH impedance
state.
An exception to this procedure occurs when the Serving
System instructs the mobile not to monitor the Busy/Idle
bits. In this event the arbitration logic can be disabled by
clearing I²C-bus register bit ABREN.
The flow of events during a Control Channel Access
attempt is as follows:
Initial state
• Transmitter disabled
• DPROC2 transmit circuitry in power-up state
• TXCTRL line HIGH.
Table 11 Digital colour code; 7-bit word
DCC1
DCC0
CODED DCC
0
0
0
0
0
0
0
0
0
0
1
0
0
1
1
1
1
1
1
0
1
1
0
0
0
1
1
1
1
1
1
1
1
1
0
0
1997 Jan 28
19