UMA1002 Datasheet, PDF (5/36 Pages) NXP Semiconductors – Data processor for cellular radio DPROC2

Philips Semiconductors
Data processor for cellular radio
(DPROC2)
Product specification
UMA1002
SYMBOL
PIN
SO28 LQFP32
DESCRIPTION
TXCTRL
INVTX
TSCAN
A0
SDA
SCL
n.c.
RXCLK
V_DDD
V_DDA
MVO
JTACS
CLKSEL
20
19 Transmitter control open-drain output used to disable the transmitter during an
RECC access failure. Output level LOW means RF disabled.
21
21 This input inverts the sense of transmitted data stream, which allows RF
modulators with high or low local oscillators to be used. The AMPS and TACS
specifications define NRZ encoded logic 1 as a LOW-to-HIGH transition in the
centre of a data bit period. The polarity of the modulated data stream depends on
the transmitter local oscillator. Input LOW means data inverted.
22
22 Test switch input, only enabled if TST = logic 1, but should have a defined state.
23
23 Input to select the least significant bit of the I²C-bus address.
24
24 Serial data input/output (I²C-bus).
25
25 Serial clock input (I²C-bus).
26
18 Not connected.
27
26 Received data clock input from the system controller.
28
27 Digital supply voltage (+3 V).
−
28 Analog supply voltage (+3 V).
−
3 Majority voting output indicating that on FOCC the first 3 received words do not
differ from each other and thus the majority decision over 5 words can already be
carried out. Because of the required speed, indication is at this pin (and not via the
I²C-bus) which can be monitored by the system controller. Output LOW means the
receiver can be switched off.
−
6 Digital input signal for JTACS, input HIGH means that data is routed from TXLINE
directly without processing to gated D/A converter (if enabled by STEN bit).
−
20 Input switch for internal divide-by-8 or divide-by-1 divider between CLKIN and
CLKOUT (internal pull-down → divide-by-1 is default if not bonded out in SO28
package).
Note
1. Must not be connected in existing applications.
1997 Jan 28
5