UMA1002 Datasheet, PDF (4/36 Pages) NXP Semiconductors – Data processor for cellular radio DPROC2

Philips Semiconductors
Data processor for cellular radio
(DPROC2)
Product specification
UMA1002
PINNING
SYMBOL
V_SSA
AGND
DEMODD
DATA
RACTRL
RESET
INVRX
RXLINE
TST
RECDATA
TACTRL
CLKIN
CLKOUT
V_SSD
TXLINE
n.c.
TXHOLD
TXCLK
BUSY/VSAT
PIN
SO28 LQFP32
DESCRIPTION
1
29 Negative analog supply (0 V). To be connected low-ohmic to V_SSD.
2
30 Internally generated analog signal ground. Voltage level = ¹â„₂V_DDA. This pin should
be connected to a blocking capacitor, no DC load allowed.
3
31 DEMODD inputs analog data and SAT signals from the RF demodulator. This pin
should normally be AC-coupled. See Chapter “AC characteristics”.
4
32 Data is an analog output which provides the Manchester encoded and filtered data
signal, SAT and signalling tone. This signal should normally be AC-coupled into the
Audio/Data summer. See Chapter “AC characteristics”.
5
1 Received audio control output. Open-drain output used to blank the audio path to
the earpiece when a sequence of dotting followed by a synchronization word or 2
synchronization words separated by 77 bits is detected. RACTRL and TACTRL
functions can be combined using one line. Output level LOW means audio muted.
6
2 Master reset input resetting all internal flip-flops to the specified state. This input
has no influence on analog parts, but must be controlled by an active HIGH
microcontroller port.
7
4 This input inverts the sense of received data stream, which allows RF
demodulators with high or low local oscillators to be used. The AMPS and TACS
specifications define NRZ encoded logic 1 as a LOW-to-HIGH transition in the
centre of a data bit period. The polarity of the demodulated data stream into
DPROC2 depends on the receiver local oscillator. Input LOW means data normal.
8
5 Received data signal output to the system controller.
9
7 Test input pin (note 1).
10
8 Output of the recovered digital data signal (note 1).
11
9 Transmitter audio control output. This open-drain output is used to blank the audio
path and enable the data path to the modulator during data bursts on the RVC.
Output level LOW means audio muted.
12
10 1.2 MHz or 9.6 MHz external master clock input. This input signal should be
accurate to 100 × 10^−6 and have a worst case 60 : 40 mark-space ratio.
13
11 Output of 1.2 MHz clock signal (for APROC) derived from CLKIN.
14
12 Negative digital supply (0 V), internally connected to substrate. To be connected
low-ohmic to V_SSA.
15
13 Open-drain bidirectional data line to the system controller (internal 100 kΩ pull-up).
16
14 Not connected.
17
15 This input holds off transmission of data when set to HIGH.
18
16 Transmitted data clock input from the system controller.
19
17 Output indicating the status of the RECC by providing output information based on
a majority decision on the last 3 consecutive Busy/Idle bits (FVC = logic 0). Output
level LOW means channel idle.
Indicating the result of the comparison of the measured SAT and the expected SAT
colour-code bits (I²C-bus register) in the voice channel mode (FVC = logic 1 and
ENSM = logic 1). Output level LOW means incoming SAT not equal to expected
SAT.
1997 Jan 28
4