UMA1002 Datasheet, PDF (18/36 Pages) NXP Semiconductors – Data processor for cellular radio DPROC2

Philips Semiconductors
Data processor for cellular radio
(DPROC2)
Product specification
UMA1002
handbook, full pagewidth
RXLINE
bit 31
bit 30
bit 29
RWIN
bit 2
bit 1
bit 0
RXCLK
t _WAIT
t _{CLK (min)}
TXLINE
TXCLK
bit 39
bit 38
th
t _su
(a)
DPROC holds TXLINE LOW
during encoder stage
buffer clear
bit 1
bit 0 ⁽²⁾
buffer busy ⁽¹⁾
t _WAIT
TWIN
MBC769
(b)
(1) The buffer time depends on whether the first or subsequent words are being loaded.
(2) The system controller should monitor the TXLINE during bit 0, if the status of TXLINE does not change from a HIGH-to-LOW on the rising edge of
TXCLK, then a framing error has occurred. This can be caused by glitches on the clock line or if an arbitration error occurred while the DPROC2
transmit register was being loaded. The system controller should recover the situation by holding TXLINE HIGH and supplying clocks on TXCLK
until TXLINE goes LOW. Then the situation should be treated as a normal channel arbitration failure as described in Section “Reverse Control
Channel Access Arbitration” - “Abort procedure (see Fig.10)”.
(a) DPROC2 to microcontroller link; receive data timing.
(b) Microcontroller to DPROC2 link; transmit data timing.
Where:
t_h > 100 ns
t_su > 500 ns.
Fig.8 Data timing diagrams.
1997 Jan 28
18