UMA1002 Datasheet, PDF (16/36 Pages) NXP Semiconductors – Data processor for cellular radio DPROC2

Philips Semiconductors
Data processor for cellular radio
(DPROC2)
Product specification
UMA1002
RECEIVED DATA SERIAL LINK
The Received Data Serial Link transfers data and control
information from DPROC2 to the System Controller.
The data is transferred on RXLINE under control of a clock
signal RXCLK, generated by the System Controller.
The system controller is informed of the arrival of a
decoded data word in the DPROC2 output register by
RXLINE being driven LOW. If the system controller
chooses to ignore the received data or only partially clock
the data out, the DPROC2 will reset the receive buffer for
the next word after the period RWIN (see Fig.8).
Data format
Each Received Data word consists of 4 bytes. The word
format is shown in Fig.7(a). The sense and function of the
fields is shown in Table 9.
Link protocol
The Received Data protocol is described by the timing
diagram Fig.8(a) and has the following parameters:
• Maximum receive window (RWIN)
– Control Channel (TACS) = 47 ms; MAJ = 0
– Control Channel (TACS) = 30.5 ms; MAJ = 1
(in FOCC only)
– Control Channel (AMPS) = 37 ms; MAJ = 0
– Control Channel (AMPS) = 23.8 ms; MAJ = 1
(in FOCC only)
• Minimum clock period (t_CLKmin) = 2 µs
• Minimum clock hold-off (t_WAIT) = 2 µs.
TRANSMIT DATA SERIAL INTERFACE
The Transmit Data Serial Link performs reception of data
from the System Controller to DPROC2 over a dedicated
line TXLINE. The transfer of data is synchronous with a
clock signal TXCLK, generated by the System Controller.
Data format
Each Transmit Data word consists of 5 bytes. The word
format is shown in Fig.7(b). The sense and function of the
fields is shown in Table 10.
Link protocol
Messages are normally up to 5 words in length on the
Reverse Control Channel and up to 2 words in length on
the Reverse Voice Channel. However, DPROC2 will
transmit messages of any word length. These must be
transmitted on the data stream without interruption. To
avoid the need for large buffer areas, a flexible protocol is
used to allow DPROC2 to control the transfer of data
words. DPROC2 has an on-chip buffer which can hold one
complete word of a message. While new words are being
loaded into DPROC2, within the time period Buffer clear to
end of TWIN, DPROC2 will maintain uninterrupted data
transmission. The System Controller can abort the
transmission of a message at any point activating the
I²C-bus signal TXRST. This signal causes the interface to
return to its power-up state and resets TXIP and TXABRT
(see Table 4). On completion of these tasks TXRST will
return to its inactive state. The Transmit Data Protocol is
described by the timing diagram shown in Fig.8(b) and has
the following parameters:
• Maximum transmit window (TWIN)
– voice channel (TACS) = 60 ms
– voice channel (AMPS) = 48 ms
– control channel (TACS) = 29 ms
– control channel (AMPS) = 23 ms
• Minimum clock period (t_CLKmin) = 2 µs
• Minimum wait period (t_WAIT) = 2 µs.
Note that TXRST will clear the transmit buffer.
1997 Jan 28
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