UMA1002 Datasheet, PDF (14/36 Pages) NXP Semiconductors – Data processor for cellular radio DPROC2

Philips Semiconductors
Data processor for cellular radio
(DPROC2)
Product specification
UMA1002
Digital circuit blocks
GENERAL
The majority of the digital circuitry within the DPROC2
device is identical for both AMPS and TACS. The
interconnections of the digital blocks discussed below are
shown in Fig.1.
DATA RECOVERY
The Data Recovery Block receives wideband Manchester
encoded data in sampled and sliced form from the
Comparator Block, on which it performs the following
functions:
• Clock recovery
• Manchester decoding
• Data regeneration.
The Clock Recovery Block extracts an 8 or 10 kHz (TACS
or AMPS) phase-locked clock signal from the Manchester
encoded data stream. This is implemented using a
digital-phase-locked-loop (PLL) which has an adjustable
‘bandwidth’ to provide both fast acquisition and low jitter.
Manchester decoding is performed by exclusive ORing the
recovered Manchester encoded data with the recovered
clock.
The NRZ data regeneration is performed by a digital
integrate and dump circuit. This consists of an up/down
counter that counts 1.2 MHz cycles during the data period.
The sense of the count is determined by the result of the
Manchester Decoder output. The number of counts is
sampled at the end of a data period. If this number
exceeds a threshold the data is latched as a logic 1
otherwise it is latched as a logic 0.
SAT DETERMINATION
The SAT Determination Block indicates which, if any, of
the valid SAT tones is detected from the recovered SAT.
The AMPS and TACS specifications require that a
determination is made at least every 250 ms.
Determination involves counting the number of cycles of
the regenerated SAT in this time period. This count is then
compared to a set of four known counts which define the
boundaries between the SAT frequencies and
SAT-not-valid events. The result is then coded into the I²C
status registers MSCC0 and MSCC1.
SAT REGENERATION
The SAT Regeneration Block generates a digital SAT
stream for transponding back to the base station.
The transponded SAT is phase-locked to the recovered
SAT by means of a second digital phase-locked-loop.
To minimize the total harmonic distortion of the output
signal the transponded SAT is then processed by a delta
modulator before being passed on to the Gated
Digital-to-Analog (D/A) converter.
DOTTING DETECTOR
The Dotting Detector Block determines whether a data
inversion (dotting) pattern has been received on the
Forward Voice Channel. The detection of data inversion
indicates that the Clock Recovery Block has acquired bit
synchronization and that the narrow bandwidth mode on
the clock recovery phase-locked-loop is selected.
This signal is also used to indicate that a data burst is
expected and activates the audio mute RACTRL, after a
Word Synchronization Block has been received, for the
duration of the burst.
SAT RECOVERY
The SAT Recovery Block receives a filtered and sliced
SAT signal which must be recovered before being routed
to the Determination and Regeneration Blocks.
The recovery is performed using a digital phase-locked
loop.
1997 Jan 28
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