UMA1002 Datasheet, PDF (15/36 Pages) NXP Semiconductors – Data processor for cellular radio DPROC2

Philips Semiconductors
Data processor for cellular radio
(DPROC2)
Product specification
UMA1002
WORD SYNCHRONIZATION DETECTOR
The Word Synchronization Block performs the following
functions:
• Frame Synchronization
• Reverse Control Channel status (B/I determination)
• Valid Serving System determination.
These functions are associated solely with the Forward
Control Channel and have no meaning on the Forward
Voice Channel.
Information in a data stream is identified by its position with
respect to a unique synchronization word.
This synchronization word is an 11-bit Barker code which
has a low probability of simulation in an error environment,
and can be easily detected. Data received is only
considered valid at times when DPROC2 has achieved
frame synchronization.
In this condition the block leaves its search mode and
enters its lock mode. This is indicated by bit WSYNC being
set HIGH. In order to achieve this two consecutive
synchronization words separated by 463 bits must be
detected. Once in lock mode, the synchronization word
detector is examined every 463 bits and only loses frame
synchronization after 5 consecutive unsuccessful
attempts at detecting the synchronization word have been
made. At this point bit WSYNC is cleared and the device is
returned to its search mode.
Information detailing the status of the Reverse Control
Channel is given by the Busy/Idle bits. These occur at
intervals of 11 bits within the frame, the first occurring
immediately following the synchronization word.
The status of the channel is determined by a majority
decision on the last three consecutive Busy/Idle bits.
FVC: After detection of 2 consecutive sync words the
circuit leaves its Search Mode and enters the Lock Mode.
The data word in between is considered as valid and
already stored for Majority Voting. Whenever a sync word
was found the incoming data stream is examined 88 bits
later for sync again. Whenever a valid sync word is
detected the following data word is given to the Majority
Voting block. After missing two consecutive sync words
the circuit goes back to the search mode (scanning for
sync every bit). If a sync word is then detected again, the
following data word is immediately accepted (and not only
after two correctly timed sync words). The detection
process of sync words is independent of the detection of
dotting. The audio mute via pin RACTRL is activated either
by receiving a sync word after detection of a dotting
sequence or by entering Lock Mode.
MAJORITY VOTING BLOCK
The Majority Voting Block performs the following functions:
• Identifying position and validity of frames in the received
data stream
• Extracting five repeats of each word from a valid frame
• Performing a bit-wise majority decision on the five
repeats of the data word.
The validity of the frames is determined by setting a
counter in operation which times out and resets the
circuitry after 920 or 463 bit periods from detecting valid
word synchronization. The time out period selected
depends on whether DPROC2 is monitoring the Forward
Voice or Control Channel respectively.
Up to five repeats of the message word are searched for
and extracted by DPROC2. On the Forward Voice
Channel the extraction of a data word for majority voting is
described in the Section “Word Synchronization Detector”.
DPROC2 enables two mechanisms for Majority Voting.
The first is based on 5 words and is described above.
The other mechanism is based on 3 consecutive identical
words and thus enabling switch-off of parts of the receiver
during reception of the remaining two words (see Table 5
and Fig.6).
ERROR CORRECTION BLOCK
The Error Correction Block performs:
• Extraction of a valid message from the Majority-Voted
Word
• Computation of the S1 and S3 syndromes
• Correction of up to one error in the word
• Communication of received data to the System
Controller via the Received Data Serial Link.
Interpretation of parity of a received word is obtained from
knowledge of the syndromes of the word. The syndromes
are calculated using feedback shift registers with two
characteristic polynomials:
1 + x + x⁶ and 1 + x + x² + x⁴ + x⁶
Once the syndromes of a received word are known, it is
possible to determine if a correctable error is present.
DPROC2 only corrects up to one error although the code
used has a Hamming distance of five. The occurrence of
two or more errors is signalled by setting the BCH error
flag, which is communicated to the System Controller via
the Received Data Serial Link.
1997 Jan 28
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