UMA1002 Datasheet, PDF (11/36 Pages) NXP Semiconductors – Data processor for cellular radio DPROC2

Philips Semiconductors
Data processor for cellular radio
(DPROC2)
Product specification
UMA1002
Table 4 Description of I²C-bus register map
REGISTER
BITS
LOGIC LEVEL
DESCRIPTION
Control Register 1
BUFEN
0
1
SERV
0
1
STS⁽¹⁾
0
1
TXRST
1
ABREN
1
0
FVC⁽²⁾
0
1
STEN
0
1
SATEN
0
1
1.2 MHz signal not available at pin CLKOUT
1.2 MHz signal is available at pin CLKOUT
serving system data stream B selected
serving system data stream A selected
TACS selected
AMPS selected
terminates a message being transmitted on the reverse channel; monostable
signal causing a reset of the message transmission circuitry and resets the
I²C-bus bits TXABRT, TXIP and clears the transmit buffer
DPROC2 has permission to abort data transmission and disable RF on the RECC
following the detection of a channel access attempt collision
no permission for above operations
control channel format selected
voice channel format selected
disables output of signalling tone to pin DATA
enables output of signalling tone to pin DATA if FVC = logic 1
disables output of SAT transponded signal to pin DATA
enables output of SAT transponded signal to pin DATA if FVC = logic 1
Control Register 2
MAJ
0
1
MR0, MR1
see Table 5
DBCH
DCFM
ENSM
ESCC0,
ESCC1
see Table 8
see Table 8
0
1
see Table 6
Status Register
WSYNC
0
1
majority voting procedure on FOCC using all 5 frame words, MVO output is always
HIGH
majority voting procedure on FOCC using the first 3 frame words, if they are all
identical the MVO pin goes LOW (see Fig.6)
determines set-up time of MVO signal with respect to beginning of the next dotting
(see Fig.6)
BCH error filter
control filler message filter
enable SAT monitoring; ESCC bits are not used
enable SAT monitoring; ESCC bits are used for following function
expected SAT colour code bits; the incoming SAT is compared to these bits, the
result (expected or not expected SAT frequency) is given out by the BUSY/VSAT
pin (when FVC = logic 1), which prevents periodical reading from the I²C-bus
status register
DPROC2 has not acquired frame synchronization in accordance with FOCC
format
DPROC2 has acquired frame synchronization in accordance with FOCC format
1997 Jan 28
11