UMA1002 Datasheet, PDF (20/36 Pages) NXP Semiconductors – Data processor for cellular radio DPROC2

Philips Semiconductors
Data processor for cellular radio
(DPROC2)
Product specification
UMA1002
Access attempt procedure
1. System Controller decides to send message⁽¹⁾.
2. System Controller drives TXCTRL LOW directly.
3. System Controller switches transmitter power-on and
waits for power-up for the transmitter module (RF
transmitter is still disabled by TXCTRL).
4. System Controller sets TXRST via I²C-bus to
DPROC2.
5. System Controller sets ABREN via I²C (if required)
allowing DPROC2 to control the transmitter.
6. System Controller determines status of Reverse
Control Channel by monitoring the Busy/Idle bit.
If busy, waits a random time then tries again.
7. System Controller releases TXCTRL allowing it to be
pulled HIGH enabling the transmitter output.
8. System Controller transfers the first word of the
message to DPROC2 via serial link⁽¹⁾.
9. DPROC2 sets I²C-bus signal TXIP and starts sending
message while monitoring Busy/Idle status.
10. If channel becomes busy before 56 bits and ABREN is
set then perform Abort Procedure.
11. If channel remains idle after 104 bits and ABREN is set
then perform Abort Procedure.
12. System controller loads the subsequent words of the
message into DPROC2 when the buffer becomes
clear as shown in Fig.8(b).
13. On completion of entire message DPROC2 clears
TXIP and 25 ms later the System Controller disables
transmitter via I²C-bus.
14. System Controller finally sends TXRST to prepare
DPROC2 for next transmission.
Abort procedure (see Fig.10)
1. DPROC2 immediately disables transmitter output by
driving TXCTRL LOW.
2. DPROC2 sets TXABRT.
3. System Controller detects failure by monitoring
TXCTRL and TXABRT.
4. System Controller disables transmitter via RF power
amplifier.
5. System Controller sends TXRST to prepare DPROC2
for next transmission.
SIGNAL TONE GENERATION (ST)
The 8 or 10 kHz (TACS or AMPS) tone generated from the
Manchester Encoding Block is used as the Signalling Tone
stream.
(1) At stage 1 the system controller may choose to preload
DPROC2 with the first word of the message and hold it from
transmission until stage 7 using the TXHOLD line. This gives
a lower time overhead between detecting an IDLE channel
and commencing the transmission. To use this feature
TXHOLD must be driven HIGH before the last bit of data has
been transferred into DPROC2. Figure 9 illustrates the
DPROC2 data transmission timing.
1997 Jan 28
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