UMA1002 Datasheet, PDF (12/36 Pages) NXP Semiconductors – Data processor for cellular radio DPROC2

Philips Semiconductors
Data processor for cellular radio
(DPROC2)
Product specification
UMA1002
REGISTER
BITS
BUSY
TXABRT
TXIP
MSCC1,
MSCC0
LOGIC LEVEL
DESCRIPTION
0
1
0
1
0
1
0
1
see Table 7
indicates the status of RECC, determined by a majority decision on the result of
the last 3 consecutive Busy/Idle bits of the FOCC and is also routed to pin
BUSY/VSAT
channel idle
channel busy
indicates the result of the comparison of the incoming SAT and the stored SAT
Colour Code bits in the Voice Channel mode and is also routed to pin BUSY/VSAT
incoming SAT not equal to expected SAT
incoming SAT equal to expected SAT
indicates that a RECC access attempt has been aborted without successful
message transmission
no access collision detected
transmission attempt aborted
no transmission on RECC or RVC in progress
data transmission by DPROC2 on RECC or RVC in progress
provides information about the current measured SAT colour code
Notes
1. Changing this register bit resets internally the receive and transmit logic circuitry.
2. Changing this register bit resets internally the receive logic circuitry.
Table 5 Set-up time of MVO signal
MR0
0
0
1
1
MR1
0
1
0
1
t_MVO (ms)
3
6
9
12
Table 6 Expected SAT colour code
ESCC1
0
0
1
1
ESCC0
0
1
0
1
SAT
FREQUENCY
(Hz)
5 970
6 000
6 030
no valid SAT
Table 7 Measured SAT colour code
MSCC1
0
0
1
1
MSCC0
0
1
0
1
SAT
FREQUENCY
(Hz)
5 970
6 000
6 030
no valid SAT
1997 Jan 28
12