UMA1002 Datasheet, PDF (23/36 Pages) NXP Semiconductors – Data processor for cellular radio DPROC2

Philips Semiconductors
Data processor for cellular radio
(DPROC2)
Product specification
UMA1002
Analog circuit blocks
GENERAL
The analog signal processing functions on DPROC2 are
implemented using switched-capacitor techniques.
The main filtering functions are operated at 300 kHz, and
these circuits are ‘interfaced’ to the continuous time and
sampled digital domains by RC active filters, passive
interpolators and comparators.
The RC sections, the Anti-Alias Filter and the Clock Filter,
are non-critical and are designed to tolerate process
spreads. The critical filtering in the SAT Filter and the
Output Filter, is performed by 300 kHz switched-capacitor
circuitry. The Passive Interpolator increases the sampling
rate from 300 kHz to 1.2 MHz. The sampled analog
signals from the Passive Interpolator is converted to a
sampled 2-state digital signal by a Comparator. The Gated
D/A converter blocks and Analog Summer block together
perform resynchronization and sub-sampling of the
digitally generated DPROC2 output signals, and
conversion to the sampled analog domain.
These analog sections of the device are shown in Fig.1.
BIAS GENERATOR
The Bias Generator generates the analog ground
reference voltage (AGND) used internally within the
DPROC2 device. To minimize noise AGND must be
externally decoupled to V_SSA as shown in Fig.12. It also
contains a current reference to generate all bias currents
for the analog circuits.
ANTI-ALIASING FILTER
The Anti-Aliasing Filter is placed before the SAT filter block
to prevent any unwanted signals or high-frequency noise
present on the DEMODD pin being aliased into the
pass-band by the sampling action of the
switched-capacitor filter. To achieve this the Anti-Aliasing
Filter is a time-continuous RC-active low-pass filter.
SAT INPUT FILTER
The SAT Input Filter is a switched-capacitor filter which
provides band-pass filtering of the SAT signals from the
DEMODD pin to improve the SAT signal-to-noise ratio
prior to recovery and transponding.
PASSIVE INTERPOLATOR
The function of the Passive Interpolator is to increase the
sampling rate at the output of the SAT filter. This reduces
the coarseness of the zero-crossing information which
would otherwise cause unacceptable isochronous
distortion in the recovered signal.
COMPARATORS
The Comparators form the analog-to-digital interface for
the received data and SAT signals from the DEMODD pin.
These comparators act as limiting amplifiers which convert
the filtered sampled analog signals into 2-state sampled
digital signals containing only the zero-crossing
information from the analog signal. To prevent unwanted
signals being processed by the digital circuitry both
comparators have a hysteresis implemented
GATED D/A CONVERTERS AND ANALOG SUMMER
The Gated D/A converters and Analog Summer form the
interface between the digital and analog circuitry on the
transmit path of DPROC2. It is at this point that the three
sampled digital signals, containing SAT, ST and encoded
digital data, are combined to form a composite signal.
The data streams are enabled by the I²C signals STEN,
SATEN and the internal signal DATAEN respectively
(DATAEN disables SAT and ST when data is being
transmitted). The digital-to-analog conversion and
sub-sampling operation is performed by the Gated D/A
converters and Analog Summer.
The typical relative signal weights applied in the summer
(with respect to the data path) are shown in Table 12.
Table 12 Typical relative signal weight
SIGNAL
ST or DATA
SAT
RELATIVE OUTPUT LEVEL
AMPS AND TACS
1.0
0.25
OUTPUT FILTER
The Output Filter is a switched-capacitor filter which
performs band-limiting of the DPROC2 output signals in
accordance with the AMPS and TACS specifications.
The required below band roll-off is achieved via external
AC-coupling from the DATA pin.
CLOCK FILTER
The Clock Noise Filter is a non-critical continuous time
RC-active low-pass filter used to remove any switching
transient residues from the output signal. It contains an
output driver stage to provide a low output impedance and
sufficient driving capability for the pin DATA.
1997 Jan 28
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