80C554 Datasheet, PDF (72/76 Pages) NXP Semiconductors – 80C51 8-bit microcontroller . 6 clock operation 16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O, 64L LQFP

Philips Semiconductors
80C51 8-bit microcontroller – 6 clock operation
16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I²C, PWM,
capture/compare, high I/O, 64L LQFP
Preliminary specification
80C554/83C554/87C554
V_DD
P1.6
P1.7
RST
STADC
V_DD
I_DD
V_DD
V_DD
P0
(NC)
CLOCK SIGNAL
XTAL2
XTAL1
V_SS
EW
EA
AV_SS
AV_ref–
SU00219
Figure 59. I_DD Test Condition, Idle Mode
All other pins are disconnected²
2. Idle Mode:
a. The following pins must be forced to V_DD: Port 0 and EW.
b. The following pins must be forced to V_SS: RST, STADC, AV_ss, AV_ref–, and EA.
c. Ports 1.6 and 1.7 should be connected to V_DD through resistors of sufficiently high value such that the sink current into these pins
cannot exceed the I_OL1 spec of these pins. These pins must not have logic 0 written to them prior to this measurement.
d. The following pins must be disconnected: XTAL2 and all pins not specified above.
V_DD–0.5
0.5V
0.7V_DD
0.2V_DD–0.1
t_CHCL
t_CLCX
t_CHCX
t_CLCH
t_CLCL
SU00220
Figure 60. Clock Signal Waveform for I_DD Tests in Active and Idle Modes
t_CLCH = t_CHCL = 5 ns
V_DD
(NC)
P1.6
P1.7
RST
STADC
XTAL2
XTAL1
V_SS
V_DD
I_DD
V_DD
V_DD
P0
EW
EA
AV_SS
AV_ref–
SU00221
Figure 61. I_DD Test Condition, Power Down Mode
All other pins are disconnected. V_DD = 2 V to 5.5 V³
3. Power Down Mode:
a. The following pins must be forced to V_DD: Port 0 and EW.
b. The following pins must be forced to V_SS: RST, STADC, XTAL1, AV_ss, AV_ref–, and EA.
c. Ports 1.6 and 1.7 should be connected to V_DD through resistors of sufficiently high value such that the sink current into these pins
cannot exceed the I_OL1 spec of these pins. These pins must not have logic 0 written to them prior to this measurement.
d. The following pins must be disconnected: XTAL2 and all pins not specified above.
2000 Nov 10
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