English
Language : 

80C554 Datasheet, PDF (30/76 Pages) NXP Semiconductors – 80C51 8-bit microcontroller . 6 clock operation 16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O, 64L LQFP
Philips Semiconductors
80C51 8-bit microcontroller – 6 clock operation
16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I2C, PWM,
capture/compare, high I/O, 64L LQFP
Preliminary specification
80C554/83C554/87C554
IEN1 (E8H)
7
ET2
(MSB)
6
ECM2
5
ECM1
4
ECM0
3
ECT3
2
ECT2
1
ECT1
0
ECT0
(LSB)
BIT
SYMBOL FUNCTION
IEN1.7
IEN1.6
IEN1.5
IEN1.4
IEN1.3
IEN1.2
IEN1.1
IEN1.0
ET2
ECM2
ECM1
ECM0
ECT3
ECT2
ECT1
ECT0
Enable Timer T2 overflow interrupt(s)
Enable T2 Comparator 2 interrupt
Enable T2 Comparator 1 interrupt
Enable T2 Comparator 0 interrupt
Enable T2 Capture register 3 interrupt
Enable T2 Capture register 2 interrupt
Enable T2 Capture register 1 interrupt
Enable T2 Capture register 0 interrupt
SU00755
In all cases, if the enable bit is 0, then the interrupt is disabled, and if the enable bit is 1, then the interrupt is enabled.
Figure 28. Interrupt Enable Register (IEN1)
IP0 (B8H)
7
–
(MSB)
BIT
IP0.7
IP0.6
IP0.5
IP0.4
IP0.3
IP0.2
IP0.1
IP0.0
6
5
4
3
2
1
PAD PS1 PS0 PT1 PX1 PT0
SYMBOL
–
PAD
PS1
PS0
PT1
PX1
PT0
PX0
FUNCTION
Unused
ADC interrupt priority level
SIO1 (I2C) interrupt priority level
SIO0 (UART) interrupt priority level
Timer 1 interrupt priority level
External interrupt 1 priority level
Timer 0 interrupt priority level
External interrupt 0 priority level
Figure 29. Interrupt Priority Register (IP0)
0
PX0
(LSB)
SU00763
IP0H (B7H)
7
–
(MSB)
6
PADH
5
PS1H
4
PS0H
3
PT1H
2
PX1H
1
PT0H
0
PX0H
(LSB)
BIT
IP0H.7
IP0H.6
IP0H.5
IP0H.4
IP0H.3
IP0H.2
IP0H.1
IP0H.0
SYMBOL
–
PADH
PS1H
PS0H
PT1H
PX1H
PT0H
PX0H
FUNCTION
Unused
ADC interrupt priority level high
SIO1 (I2C) interrupt priority level high
SIO0 (UART) interrupt priority level high
Timer 1 interrupt priority level high
External interrupt 1 priority level high
Timer 0 interrupt priority level high
External interrupt 0 priority level high
Figure 30. Interrupt Priority Register High (IP0H)
SU00983
2000 Nov 10
30