80C554 Datasheet, PDF (66/76 Pages) NXP Semiconductors – 80C51 8-bit microcontroller . 6 clock operation 16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O, 64L LQFP

Philips Semiconductors
80C51 8-bit microcontroller – 6 clock operation
16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I²C, PWM,
capture/compare, high I/O, 64L LQFP
Preliminary specification
80C554/83C554/87C554
AC ELECTRICAL CHARACTERISTICS
V_DD and T_amb minimum and maximum, per device specifications table; V_SS = 0 V; C_L = 100 pF for Port 0, ALE and PSEN; C_L = 80 pF for all
other outputs unless otherwise specified.
16 MHz CLOCK
VARIABLE CLOCK
SYMBOL FIGURE
PARAMETER
MIN MAX
MIN
MAX
UNIT
External Program Memory
1/f_CLK
49
System clock frequency, see Note 1
t_LHLL
49
ALE pulse width
t_AVLL
49
Address valid to ALE LOW
t_LLAX
49
Address hold after ALE LOW
t_LLIV
49
ALE LOW to valid instruction in
t_LLPL
49
ALE LOW to PSEN LOW
t_PLPH
49
PSEN pulse width
t_PLIV
49
PSEN LOW to valid instruction in
t_PXIX
49
Input instruction hold after PSEN
t_PXIZ
49
Input instruction float after PSEN
t_AVIV
49
Address to valid instruction in
t_PLAZ
49
PSEN LOW to address float
External Data Memory
37.5
6.25
6.25
–
6.25
48.75
–
0
–
–
–
–
–
–
60
–
–
33.75
–
6.25
76.25
10
3.5
t_CLK–25
0.5 t_CLK–25
0.5 t_CLK–25
–
0.5 t_CLK–25
1.5 t_CLK–45
–
0
–
–
–
16
–
–
–
2 t_CLK–65
–
–
1.5 t_CLK–60
–
0.5 t_CLK–25
2.5 t_CLK–80
10
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t_RLRH
50, 51
t_WLWH
50, 51
t_RLDV
50, 51
t_RHDX
50, 51
t_RHDZ
50, 51
t_LLDV
50, 51
t_AVDV
50, 51
t_LLWL
50, 51
t_AVWL
50, 51
t_QVWX
50, 51
t_WHQX
51
t_QVWH
50, 51
t_RLAZ
50, 51
t_WHLH
50, 51
External Clock
RD pulse width
WR pulse width
RD LOW to valid data in
Data hold after RD
Data float after RD
ALE LOW to valid data in
Address to valid data in
ALE LOW to RD or WR LOW
Address valid to RD low or WR LOW
Data valid to WR transition
Data hold after WR
Data valid time WR HIGH
RD LOW to address float
RD or WR HIGH to ALE HIGH
87.5
–
3 t_CLK–100
–
ns
87.5
–
3 t_CLK–100
–
ns
–
66.25
–
2.5 t_CLK–90
ns
0
–
0
–
ns
–
42.5
–
t_CLK–20
ns
–
100
–
4 t_CLK–150
ns
–
116.25
–
4.5 t_CLK–165
ns
43.75 143.75 1.5 t_CLK–50
1.5 t_CLK+50
ns
50
–
2 t_CLK–75
–
ns
1.25
–
0.5 t_CLK–30
–
ns
6.25
–
0.5 t_CLK–25
–
ns
88.75
–
3.5 t_CLK–130
–
ns
–
0
–
0
ns
6.25 56.25
0.5 t_CLK–25
0.5 t_CLK+25
ns
t_CHCX
52
High time
t_CLCX
52
Low time
t_CLCH
52
Rise time
t_CHCL
52
Fall time
UART Timing – Shift Register Mode
33.3
50
t_CLK 0.4
t_CLK 0.6
ns
33.3
50
t_CLK 0.4
t_CLK 0.6
ns
–
20
–
20
ns
–
20
–
20
ns
t_XLXL
t_QVXH
t_XHQX
t_XHDX
t_XHDV
53
Serial port clock cycle time
53
Output data setup to clock rising edge
53
Output data hold after clock rising edge
53
Input data hold after clock rising edge
53
Clock rising edge to input data valid
500
–
6 t_CLK
–
ns
179.5
–
5 t_CLK –133
–
ns
32.5
–
t_CLK–30
–
ns
0
–
0
–
ns
–
179.5
–
5 t_CLK–133
ns
2000 Nov 10
66