80C554 Datasheet, PDF (6/76 Pages) NXP Semiconductors – 80C51 8-bit microcontroller . 6 clock operation 16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O, 64L LQFP

Philips Semiconductors
80C51 8-bit microcontroller – 6 clock operation
16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I²C, PWM,
capture/compare, high I/O, 64L LQFP
Preliminary specification
80C554/83C554/87C554
PIN DESCRIPTION (Continued)
PIN NO.
MNEMONIC
LQFP TYPE
NAME AND FUNCTION
P4.0-P4.7
14–21
14–19
20, 21
I/O Port 4: 8-bit programmable I/O port. Alternate functions include:
O CMSR0-CMSR5 (P4.0-P4.5): Timer T2 compare and set/reset outputs on a match with timer T2.
O CMT0, CMT1 (P4.6, P4.7): Timer T2 compare and toggle outputs on a match with timer T2.
Port 4 has four modes selected on a per bit basis by writing to the P4M1 and P4M2 registers as
follows:
P4M1.x
0
0
1
1
P4M2.x
0
1
0
1
Mode Description
Pseudo-bidirectional (standard c51 configuration; default)
Push-Pull
High impedance
Open drain
P5.0-P5.6
2–8
I
Port 5: 8-bit input port.
ADC0-ADC7 (P5.0-P5.7): Alternate function: Seven input channels to the ADC.
RST
22
I/O Reset: Input to reset the 87C554. It also provides a reset pulse as output when timer T3 overflows.
XTAL1
40
I
Crystal Input 1: Input to the inverting amplifier that forms the oscillator, and input to the internal
clock generator. Receives the external clock signal when an external oscillator is used.
XTAL2
39
O Crystal Input 2: Output of the inverting amplifier that forms the oscillator. Left open-circuit when an
external clock is used.
V_SS
PSEN
41–42
51
I
Digital ground.
O Program Store Enable: Active-low read strobe to external program memory.
ALE/PROG
52
O Address Latch Enable: Latches the low byte of the address during accesses to external memory.
It is activated every six oscillator periods. During an external data memory access, one ALE pulse
is skipped. ALE can drive up to eight LS TTL inputs and handles CMOS inputs without an external
pull-up. This pin is also the program pulse input (PROG) during EPROM programming.
EA/V_PP
53
I External Access: When EA is held at TTL level high, the CPU executes out of the internal program
ROM provided the program counter is less than 16,384. When EA is held at TTL low level, the CPU
executes out of external program memory. EA is not allowed to float. This pin also receives the
12.75 V programming supply voltage (V_PP) during EPROM programming.
AV_REF–
62
I
Analog to Digital Conversion Reference Resistor: Low-end.
AV_REF+
63
I
Analog to Digital Conversion Reference Resistor: High-end.
AV_SS
64
I
Analog Ground
AV_DD
1
I
Analog Power Supply
NOTE:
1. To avoid “latch-up” effect at power-on, the voltage on any pin at any time must not be higher or lower than V_DD + 0.5 V or V_SS – 0.5 V,
respectively.
2000 Nov 10
6