80C554 Datasheet, PDF (33/76 Pages) NXP Semiconductors – 80C51 8-bit microcontroller . 6 clock operation 16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O, 64L LQFP

Philips Semiconductors
80C51 8-bit microcontroller – 6 clock operation
16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I²C, PWM,
capture/compare, high I/O, 64L LQFP
Preliminary specification
80C554/83C554/87C554
I²C bus
V_DD
R_P
R_P
SDA
SCL
P1.7/SDA P1.6/SCL
8XC554
OTHER DEVICE WITH
I²C INTERFACE
OTHER DEVICE WITH
I²C INTERFACE
Figure 33. Typical I²C Bus Configuration
SU00964
SDA
MSB
SLAVE ADDRESS
R/W
DIRECTION
BIT
ACKNOWLEDGMENT
SIGNAL FROM RECEIVER
ACKNOWLEDGMENT
SIGNAL FROM RECEIVER
CLOCK LINE HELD LOW WHILE
INTERRUPTS ARE SERVICED
STOP
CONDITION
REPEATED
START
CONDITION
SCL
S
1
2
START
CONDITION
7
8
9
ACK
1
2
3–8
9
ACK
REPEATED IF MORE BYTES
ARE TRANSFERRED
Figure 34. Data Transfer on the I²C Bus
P/S
SU00965
SIO1 Implementation and Operation: Figure 35 shows how the
on-chip I²C bus interface is implemented, and the following text
describes the individual blocks.
INPUT FILTERS AND OUTPUT STAGES
The input filters have I²C compatible input levels. If the input voltage
is less than 1.5 V, the input logic level is interpreted as 0; if the input
voltage is greater than 3.0 V, the input logic level is interpreted as 1.
Input signals are synchronized with the internal clock (f_OSC/2), and
spikes shorter than three oscillator periods are filtered out.
The output stages consist of open drain transistors that can sink
3 mA at V_OUT < 0.4 V. These open drain outputs do not have
clamping diodes to V_DD. Thus, if the device is connected to the I²C
bus and V_DD is switched off, the I²C bus is not affected.
ADDRESS REGISTER, S1ADR
This 8-bit special function register may be loaded with the 7-bit slave
address (7 most significant bits) to which SIO1 will respond when
programmed as a slave transmitter or receiver. The LSB (GC) is
used to enable general call address (00H) recognition.
COMPARATOR
The comparator compares the received 7-bit slave address with its
own slave address (7 most significant bits in S1ADR). It also
compares the first received 8-bit byte with the general call address
(00H). If an equality is found, the appropriate status bits are set and
an interrupt is requested.
SHIFT REGISTER, S1DAT
This 8-bit special function register contains a byte of serial data to
be transmitted or a byte which has just been received. Data in
S1DAT is always shifted from right to left; the first bit to be
transmitted is the MSB (bit 7) and, after a byte has been received,
the first bit of received data is located at the MSB of S1DAT. While
data is being shifted out, data on the bus is simultaneously being
shifted in; S1DAT always contains the last byte present on the bus.
Thus, in the event of lost arbitration, the transition from master
transmitter to slave receiver is made with the correct data in S1DAT.
2000 Nov 10
33