80C554 Datasheet, PDF (27/76 Pages) NXP Semiconductors – 80C51 8-bit microcontroller . 6 clock operation 16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O, 64L LQFP

Philips Semiconductors
80C51 8-bit microcontroller – 6 clock operation
16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I²C, PWM,
capture/compare, high I/O, 64L LQFP
Preliminary specification
80C554/83C554/87C554
10-Bit ADC Resolution and Analog Supply: Figure 24 shows how
the ADC is realized. The ADC has its own supply pins (AV_DD and
AV_SS) and two pins (Vref+ and Vref–) connected to each end of the
DAC’s resistance-ladder. The ladder has 1023 equally spaced taps,
separated by a resistance of “R”. The first tap is located 0.5 x R
above Vref–, and the last tap is located 1.5 x R below Vref+. This
gives a total ladder resistance of 1024 x R. This structure ensures
that the DAC is monotonic and results in a symmetrical quantization
error as shown in Figure 26.
For input voltages between Vref– and (Vref–) + 1/2 LSB, the 10-bit
result of an A/D conversion will be 00 0000 0000B = 000H. For input
voltages between (Vref+) – 3/2 LSB and Vref+, the result of a
conversion will be 11 1111 1111B = 3FFH. AVref+ and AVref– may
be between AV_DD + 0.2 V and AV_SS – 0.2 V. AVref+ should be
positive with respect to AVref–, and the input voltage (Vin) should be
between AVref+ and AVref–. If the analog input voltage range is from
2 V to 4 V, then 10-bit resolution can be obtained over this range if
AVref+ = 4 V and AVref– = 2 V.
The result can always be calculated from the following formula:
Result + 1024
V_IN * AV_ref*
AV_ref) * AV_ref*
Power Reduction Modes
The 8xC554 has two reduced power modes of operation: the idle
mode and the power-down mode. These modes are entered by
setting bits in the PCON special function register. When the 8xC554
enters the idle mode, the following functions are disabled:
CPU
Timer T2
PWM0, PWM1
ADC
(halted)
(halted and reset)
(reset; outputs are high)
(may be enabled for operation in Idle mode
by setting bit AIDC (AUXR1.6) ).
In idle mode, the following functions remain active:
Timer 0
Timer 1
Timer T3
SIO0 SIO1
External interrupts
When the 8xC554 enters the power-down mode, the oscillator is
stopped. The power-down mode is entered by setting the PD bit in
the PCON register. The PD bit can only be set if the EW input is tied
HIGH.
AV_ref+
R/2
R
R
R
TOTAL RESISTANCE
= 1023R + 2 x R/
= 1024R
1023
1022
1021
DECODER
MSB
SUCCESSIVE
APPROXIMATION
REGISTER
SUCCESSIVE
APPROXIMATION
CONTROL LOGIC
START
3
2
R
1
R
0
LSB
R/2
V_ref
AV_ref–
V_in
Value 0000 0000 00
Value 1111 1111 11
–
COMPARATOR
+
is output for voltages V_ref– to (V_ref– + 1/2 LSB)
is output for voltages (V_ref+ – 3/2 LSB) to V_ref+
Figure 24. ADC Realization
READY
SU00961
2000 Nov 10
27