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80C554 Datasheet, PDF (67/76 Pages) NXP Semiconductors – 80C51 8-bit microcontroller . 6 clock operation 16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O, 64L LQFP
Philips Semiconductors
80C51 8-bit microcontroller – 6 clock operation
16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I2C, PWM,
capture/compare, high I/O, 64L LQFP
Preliminary specification
80C554/83C554/87C554
Table 11. I2C-bus interface timing
All values referred to VIH(min) and VIL(max) levels; see Figure 565.
SYMBOL
tHD;STA
tLOW
tHIGH
tRC
tFC
tSU;DAT1
tSU;DAT2
tSU;DAT3
tHD;DAT
tSU;STA
tSU;STO
tBUF
tRD
tFD
PARAMETER
START condition hold time
LOW period of the SCL clock
HIGH period of the SCL clock
Rise time of SCL signals
Fall time of SCL signals
Data set-up time
SDA set-up time (before repeated START condition)
SDA set-up time (before STOP condition)
Data hold time
Set-up time for a repeated START condition
Set-up time for STOP condition
Bus free time between
Rise time of SDA signals
Fall time of SDA signals
I2C-BUS
INPUT
OUTPUT
≥ 7 tCLK
≥ 8 tCLK
≥ 7 tCLK
≤ 1 µs
≤ 0.3 µs
> 4.0 µs1
> 4.7 µs1
> 4.0 µs1
–2
< 0.3 µs3
≥ 250 ns
≥ 250 ns
> 10 tCLK–tRD
> 1 µs1
≥ 250 ns
≥ 0 ns
≥ 7 tCLK
≥ 7 tCLK
≥ 7 tCLK
≤ 1 µs
≤ 0.3 µs
> 4 tCLK
> 4 tCLK–tFC
> 4.7 µs1
> 4.0 µs1
> 4.7 µs1
–2
< 0.3 µs3
NOTES
1. At 100 kbit/s. At other bit rates this value is inversely proportional to the bit-rate of 100 kbit/s.
2. Determined by the external bus-line capacitance and the external bus-line pull-resistor, this must be < 1 µs.
3. Spikes of the SDA and SCL lines with a duration of less than 3 tCLK will be filtered out. Maximum capacitance on bus-lines SDA and
SCL = 400 pF.
4. tCLK = 1/fCLK = one oscillator clock period at pin XTAL1. For 83 ns < tCLK < 285 ns (12 MHz > fCLK > 3.5 MHz) the SI01 interface meets the
I2C-bus specification for bit-rates up to 100 kbit/s.
5. These values are guaranteed but not 100% production tested.
6. See application note AN457 for external memory interface.
7. Parts are guaranteed to operate down to 0Hz.
2000 Nov 10
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