80C554 Datasheet, PDF (21/76 Pages) NXP Semiconductors – 80C51 8-bit microcontroller . 6 clock operation 16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O, 64L LQFP

Philips Semiconductors
80C51 8-bit microcontroller – 6 clock operation
16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I²C, PWM,
capture/compare, high I/O, 64L LQFP
Preliminary specification
80C554/83C554/87C554
Timer T3, The Watchdog Timer
In addition to Timer T2 and the standard timers, a watchdog timer is
also incorporated on the 8xC554. The purpose of a watchdog timer
is to reset the microcontroller if it enters erroneous processor states
(possibly caused by electrical noise or RFI) within a reasonable
period of time. An analogy is the “dead man’s handle” in railway
locomotives. When enabled, the watchdog circuitry will generate a
system reset if the user program fails to reload the watchdog timer
within a specified length of time known as the “watchdog interval.”
Watchdog Circuit Description: The watchdog timer (Timer T3)
consists of an 8-bit timer with an 11-bit prescaler as shown in
Figure 18. The prescaler is fed with a signal whose frequency is 1/6
the oscillator frequency (0.5 MHz with a 12 MHz oscillator). The 8-bit
timer is incremented every “t” seconds, where:
t = 6 × 2048 × 1/f_OSC
(= 0.75 ms at f_OSC = 16 MHz; = 0.5 ms at f_OSC = 24 MHz)
If the 8-bit timer overflows, a short internal reset pulse is generated
which will reset the 8xC554. A short output reset pulse is also
generated at the RST pin. This short output pulse (3 machine
cycles) may be destroyed if the RST pin is connected to a capacitor.
This would not, however, affect the internal reset operation.
Watchdog operation is activated when external pin EW is tied low.
When EW is tied low, it is impossible to disable the watchdog
operation by software.
How to Operate the Watchdog Timer: The watchdog timer has to
be reloaded within periods that are shorter than the programmed
watchdog interval; otherwise the watchdog timer will overflow and a
system reset will be generated. The user program must therefore
continually execute sections of code which reload the watchdog
timer. The period of time elapsed between execution of these
sections of code must never exceed the watchdog interval. When
using a 16 MHz oscillator, the watchdog interval is programmable
between 0.75 ms and 196 ms. When using a 24 MHz oscillator, the
watchdog interval is programmable between 0.5 ms and 127.5 ms.
In order to prepare software for watchdog operation, a programmer
should first determine how long his system can sustain an
erroneous processor state. The result will be the maximum
watchdog interval. As the maximum watchdog interval becomes
shorter, it becomes more difficult for the programmer to ensure that
the user program always reloads the watchdog timer within the
watchdog interval, and thus it becomes more difficult to implement
watchdog operation.
The programmer must now partition the software in such a way that
reloading of the watchdog is carried out in accordance with the above
requirements. The programmer must determine the execution times
of all software modules. The effect of possible conditional branches,
subroutines, external and internal interrupts must all be taken into
account. Since it may be very difficult to evaluate the execution
times of some sections of code, the programmer should use worst
case estimations. In any event, the programmer must make sure
that the watchdog is not activated during normal operation.
The watchdog timer is reloaded in two stages in order to prevent
erroneous software from reloading the watchdog. First PCON.4
(WLE) must be set. The T3 may be loaded. When T3 is loaded,
PCON.4 (WLE) is automatically reset. T3 cannot be loaded if
PCON.4 (WLE) is reset. Reload code may be put in a subroutine as
it is called frequently. Since Timer T3 is an up-counter, a reload
value of 00H gives the maximum watchdog interval (255 ms with a
12 MHz oscillator), and a reload value of 0FFH gives the minimum
watchdog interval (1 ms with a 12 MHz oscillator).
In the idle mode, the watchdog circuitry remains active. When
watchdog operation is implemented, the power-down mode cannot
be used since both states are contradictory. Thus, when watchdog
operation is enabled by tying external pin EW low, it is impossible to
enter the power-down mode, and an attempt to set the power-down
bit (PCON.1) will have no effect. PCON.1 will remain at logic 0.
f_OSC/6
EW
PRESCALER (11-BIT)
CLEAR
WRITE T3
INTERNAL BUS
TIMER T3 (8-BIT)
LOAD LOADEN
OVERFLOW
INTERNAL
RESET
V_DD
P
RST
CLEAR
WLE
PCON.4
PD
LOADEN
PCON.1
R_RST
INTERNAL BUS
Figure 18. Watchdog Timer
SU00955
2000 Nov 10
21