80C554 Datasheet, PDF(20/76 Page) NXP Semiconductors – 80C51 8-bit microcontroller . 6 clock operation 16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O, 64L LQFP

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80C554 Datasheet, PDF (20/76 Pages) NXP Semiconductors – 80C51 8-bit microcontroller . 6 clock operation 16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O, 64L LQFP

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Philips Semiconductors

80C51 8-bit microcontroller â 6 clock operation

16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I2C, PWM,

capture/compare, high I/O, 64L LQFP

Preliminary specification

80C554/83C554/87C554

STE (EEH) TG47

(MSB)

BIT

STE.7

STE.6

STE.5

STE.4

STE.3

STE.2

STE.1

STE.0

TG46

SP45

SP44

SP43

SP42

SP41

SP40

Reset Value = C0H

(LSB)

SYMBOL FUNCTION

TG47

TG46

SP45

SP44

SP43

SP42

SP41

SP40

Toggle flip-flops

If â1â then P4.5 is set on a match between CM0 and Timer T2

If â1â then P4.4 is set on a match between CM0 and Timer T2

If â1â then P4.3 is set on a match between CM0 and Timer T2

If â1â then P4.2 is set on a match between CM0 and Timer T2

If â1â then P4.1 is set on a match between CM0 and Timer T2

If â1â then P4.0 is set on a match between CM0 and Timer T2

SU01087

Figure 16. Set Enable Register (STE)

TM2IR (C8H) T2OV CMI2 CMI1 CMI0 CTI3 CTI2 CTI1

(MSB)

BIT

SYMBOL FUNCTION

TM2IR.7

TM2IR.6

TM2IR.5

TM2IR.4

TM2IR.3

TM2IR.2

TM2IR.1

TM2IR.0

T2OV

CMI2

CMI1

CMI0

CTI3

CTI2

CTI1

CTI0

Timer T2 16-bit overflow interrupt flag

CM2 interrupt flag

CM1 interrupt flag

CM0 interrupt flag

CT3 interrupt flag

CT2 interrupt flag

CT1 interrupt flag

CT0 interrupt flag

CTI0

(LSB)

Reset Value = 00H

Interrupt Flag Register (TM2IR)

IP1 (F8H)

PT2

(MSB)

BIT

IP1.7

IP1.6

IP1.5

IP1.4

IP1.3

IP1.2

IP1.1

IP1.0

PCM2 PCM1 PCM0 PCT3 PCT2 PCT1 PCT0

SYMBOL FUNCTION

(LSB)

PT2

PCM2

PCM1

PCM0

PCT3

PCT2

PCT1

PCT0

Timer T2 overflow interrupt(s) priority level

Timer T2 comparator 2 interrupt priority level

Timer T2 comparator 1 interrupt priority level

Timer T2 comparator 0 interrupt priority level

Timer T2 capture register 3 interrupt priority level

Timer T2 capture register 2 interrupt priority level

Timer T2 capture register 1 interrupt priority level

Timer T2 capture register 0 interrupt priority level

Reset Value = 00H

Timer 2 Interrupt Priority Register (IP1)

Figure 17. Interrupt Flag Register (TM2IR) and Timer T2 Interrupt Priority Register (IP1)

SU01088

2000 Nov 10

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